Abstract: An amplifier includes a fault protection control circuit biased from the signal pin and a fault protection circuit including a first PMOS transistor and a second PMOS transistor. The sources and bodies of the first and second PMOS transistors can be connected to one another, the drain of the first PMOS transistor can be connected to the amplifier's output, and the drain of the second PMOS transistor can be connected to a signal pin. During normal operating conditions, the fault protection control circuit can turn on the first and second PMOS transistors. However, the fault protection control circuit can turn off the first PMOS transistor and turn on the second PMOS transistor when an overvoltage condition is detected, and can turn on the first PMOS transistor and turn off the second PMOS transistor when an undervoltage condition is detected, even when the integrated circuit is unpowered.

Abstract: An amplifier includes a fault protection control circuit biased from the signal pin and a fault protection circuit including a first PMOS transistor and a second PMOS transistor. The sources and bodies of the first and second PMOS transistors can be connected to one another, the drain of the first PMOS transistor can be connected to the amplifier's output, and the drain of the second PMOS transistor can be connected to a signal pin. During normal operating conditions, the fault protection control circuit can turn on the first and second PMOS transistors. However, the fault protection control circuit can turn off the first PMOS transistor and turn on the second PMOS transistor when an overvoltage condition is detected, and can turn on the first PMOS transistor and turn off the second PMOS transistor when an undervoltage condition is detected, even when the integrated circuit is unpowered.

Abstract: A signal buffer amplifier with high linearity is provided. A circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal. The circuit also includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal coupled to the first source terminal. The circuit further includes a first signal path coupled in between a signal input and the first gate terminal, a second signal path coupled in between the signal input and the second gate terminal, and a signal output coupled to the second source terminal. The first signal path includes a filter.

Abstract: In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.

Abstract: A signal buffer amplifier with high linearity is provided. A circuit includes a first transistor having a first gate terminal, a first source terminal, and a first drain terminal. The circuit also includes a second transistor having a second gate terminal, a second source terminal, and a second drain terminal, the second drain terminal coupled to the first source terminal. The circuit further includes a first signal path coupled in between a signal input and the first gate terminal, a second signal path coupled in between the signal input and the second gate terminal, and a signal output coupled to the second source terminal. The first signal path includes a filter.

Abstract: In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.