Patents by Inventor MIN-SOO JANG
MIN-SOO JANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250061103Abstract: A system for accessing ledger information by using common keyset information according to the present invention comprises: a transaction packer for adding key information corresponding to a transaction request to a generated transaction proposal; a transaction aggregator for generating common transaction batch information and common keyset information corresponding to the transaction proposal according to the key information included in the transaction proposal received from the transaction packer, and transmitting the common transaction batch information and the common keyset information to each execution node group distinguished and predesignated with regard to the common transaction batch information; at least one transaction executor for executing a simulation regarding the transaction proposals included in the common transaction batch information transmitted from the transaction aggregator, which belongs to the execution node group, and transferring the common keyset information; and a ledger manager forType: ApplicationFiled: November 17, 2022Publication date: February 20, 2025Applicants: LSWARE INC., PPUZZL GROUP INC.Inventors: Min Soo KIM, Dong Myung SHIN, Yong Joon JOE, Sung Il JANG
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Publication number: 20250061450Abstract: A ledger information access system having a plurality of storage spaces, according to the present invention, comprises: a transaction packer for adding, to generated transaction proposals, key information corresponding to a transaction request; a transaction aggregator, which separates common keyset information from common transaction batch information according to the common transaction batch information, so as to transmit each to a predefined execution node group; at least one transaction executor, which belongs to the execution node group, executes a simulation for transaction proposals included in the common transaction batch information transmitted from the transaction aggregator, and transmits the common keyset information; and a ledger manager which includes a plurality of storage spaces for storing each of a plurality of part blocks in which pieces of transaction information constituting one block connected to a blockchain are distributed, and which reads, from the plurality of storage spaces, piecesType: ApplicationFiled: November 22, 2022Publication date: February 20, 2025Applicants: LSWARE INC., PPUZZL GROUP INC.Inventors: Min Soo KIM, Dong Myung SHIN, Yong Joon JOE, Sung Il JANG
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Publication number: 20250054448Abstract: A display device includes a first pixel region including a plurality of first pixels and a plurality of first gate control lines coupled to the first pixels, and a second pixel region spaced apart from the first pixel region. The second pixel region includes a plurality of second pixels and a plurality of second gate control lines coupled to the second pixels. The display device further includes a first non-pixel region disposed between the first pixel region and the second pixel region, and a first coupling line disposed in the first non-pixel region. The first coupling line commonly couples at least two first gate control lines and at least two second gate control lines.Type: ApplicationFiled: October 30, 2024Publication date: February 13, 2025Inventors: MI HAE KIM, MIN KYU WOO, YOUNG TAEG JUNG, HYUN CHOL BANG, SANG WON SEOK, HWAN SOO JANG, JU HEE HYEON
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Patent number: 10692561Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.Type: GrantFiled: July 11, 2018Date of Patent: June 23, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-soo Jang, Eunsung Seo, Seungjun Bae
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Patent number: 10339995Abstract: Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.Type: GrantFiled: December 4, 2017Date of Patent: July 2, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-geun Do, Jong-ho Lee, Chan-yong Lee, Min-soo Jang
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Patent number: 10318469Abstract: A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.Type: GrantFiled: February 12, 2015Date of Patent: June 11, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Min-Soo Jang, Gong-Heum Han, Chul-Sung Park, Jang-Woo Ryu, Chang-Yong Lee, Tae-Seong Jang
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Publication number: 20190139596Abstract: A semiconductor memory device includes a cell array that includes a plurality of DRAM cells to store data, and refresh control logic that refreshes the plurality of DRAM cells depending on access scenario information provided from an outside. The refresh control logic determines a refresh time of the plurality of DRAM cells with reference to the access scenario information and a retention characteristic of the plurality of DRAM cells and refreshes the plurality of DRAM cells depending on the determined refresh time.Type: ApplicationFiled: July 11, 2018Publication date: May 9, 2019Inventors: Min-soo JANG, Eunsung SEO, SEUNGJUN BAE
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Publication number: 20180190341Abstract: Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.Type: ApplicationFiled: December 4, 2017Publication date: July 5, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Sung-geun DO, Jong-ho LEE, Chan-yong LEE, Min-soo JANG
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Patent number: 9502132Abstract: An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.Type: GrantFiled: June 7, 2013Date of Patent: November 22, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Soo Jang, Young-hun Seo, Chan-yong Lee
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Patent number: 9367906Abstract: Disclosed are a system and a method for compositing various images that minimize a brightness difference in connection areas of various images by using a clustering technique at the time of compositing various images. The method for compositing various images may include receiving two or more input images; compositing the two or more input images into one composite image; calculating a brightness distribution degree; calculating representative brightness values; determining clustering; calculating a correction target value; and calculating a correction value of an increase/decrease curve.Type: GrantFiled: February 28, 2014Date of Patent: June 14, 2016Assignee: Hyundai Mobis Co., Ltd.Inventors: Min Soo Jang, Ji Won Seo
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Publication number: 20160159281Abstract: Disclosed is a vehicle, including a display device; one or more cameras; and a controller configured to combine a plurality of images received from the one or more cameras and switch the combined image to a top view image to generate an around view image, detect an object from at least one of the plurality of images and the around view image, determine a weighted value of two images obtained from two cameras of the one or more cameras when an object is located in an overlapping area in views of the two cameras, assign a weighted value to a specific image of the two images from the two cameras with the overlapping area, and display the specific image with the assigned weighted value and the around view image on the display device.Type: ApplicationFiled: November 11, 2015Publication date: June 9, 2016Inventors: Min soo JANG, Sung joo LEE, Sea young HEO
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Publication number: 20150242352Abstract: A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.Type: ApplicationFiled: February 12, 2015Publication date: August 27, 2015Inventors: MIN-SOO JANG, GONG-HEUM HAN, CHUL-SUNG PARK, JANG-WOO RYU, CHANG-YONG LEE, TAE-SEONG JANG
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Publication number: 20150049950Abstract: Disclosed are a system and a method for compositing various images that minimize a brightness difference in connection areas of various images by using a clustering technique at the time of compositing various images. The method for compositing various images may include receiving two or more input images; compositing the two or more input images into one composite image; calculating a brightness distribution degree; calculating representative brightness values; determining clustering; calculating a correction target value; and calculating a correction value of an increase/decrease curve.Type: ApplicationFiled: February 28, 2014Publication date: February 19, 2015Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Min Soo JANG, Ji Won SEO
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Publication number: 20140022855Abstract: An antifuse memory device includes an antifuse memory cell, a reference current generation unit, and a comparison unit. The antifuse memory cell includes an antifuse. The reference current generation unit provides a reference current selected from a plurality of reference currents. The comparison unit compares an intensity of a cell current flowing through the antifuse with an intensity of the reference current and provides an output signal corresponding to a result of the comparison.Type: ApplicationFiled: June 7, 2013Publication date: January 23, 2014Inventors: MIN-SOO JANG, Young-hun Seo, Chan-yong Lee