Patents by Inventor Min-Soon Hwang

Min-Soon Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10511292
    Abstract: Disclosed is an oscillator including: a digital to analog converter configured to convert a received control code into an analog voltage and output the converted analog voltage; a mirror circuit configured to adjust a current of a common output node to which the analog voltage is applied; and a periodic signal output circuit configured to output a periodic signal having a frequency according to the analog voltage, in which the digital to analog converter, the mirror circuit, and the periodic signal output circuit are implemented with tri-state inverters.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: December 17, 2019
    Assignee: SK hynix Inc.
    Inventor: Min Soon Hwang
  • Publication number: 20180351508
    Abstract: Disclosed is an oscillator including: a digital to analog converter configured to convert a received control code into an analog voltage and output the converted analog voltage; a mirror circuit configured to adjust a current of a common output node to which the analog voltage is applied; and a periodic signal output circuit configured to output a periodic signal having a frequency according to the analog voltage, in which the digital to analog converter, the mirror circuit, and the periodic signal output circuit are implemented with tri-state inverters.
    Type: Application
    Filed: November 9, 2017
    Publication date: December 6, 2018
    Inventor: Min Soon HWANG
  • Patent number: 9160520
    Abstract: Provided are a serializer that synchronizes data with a clock by using an inversion clock and a high speed serializing apparatus using both a serializer and a serializer including shift registers. Such a serializer may include a first synchronization unit suitable for synchronizing input data with a first synchronization clock, a multiplexer suitable for serializing output data of the first synchronization unit based on the first synchronization clock, and a second synchronization unit suitable for synchronizing output data of the multiplexer with a second synchronization clock which is different from the first synchronization clock in frequency.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: October 13, 2015
    Assignee: SK Hynix Inc.
    Inventors: Yong-Seok Hwang, Sung-Jin Lee, Min-Soon Hwang