Patents by Inventor Minsu SEOL

Minsu SEOL has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12727206
    Abstract: A semiconductor device may include a channel layer including a two-dimensional (2D) semiconductor material, a gate insulating layer on a center portion of the channel layer, a gate electrode on the gate insulating layer, and a first conductive layer and a second conductive layer respectively contacting opposite sides of the channel layer. Each of the first and second conductive layers may include metal boride.
    Type: Grant
    Filed: May 22, 2023
    Date of Patent: September 1, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joungeun Yoo, Changhyun Kim, Kyung-Eun Byun, Minsu Seol, Keunwook Shin, Eunkyu Lee
  • Patent number: 12727190
    Abstract: A semiconductor device may include a first electrode and a second electrode on a substrate and arranged perpendicular to a surface of the substrate, a plurality of channel layers between the first electrode and the second electrode, and a gate electrode surrounding the plurality of channel layers. The plurality of channel layers may be inclined with respect to a direction from the first electrode to the second electrode. An electronic device may include the semiconductor device.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: September 1, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eunkyu Lee, Keunwook Shin, Minsu Seol
  • Patent number: 12727220
    Abstract: A semiconductor device including a two-dimensional material and a method of manufacturing the same are provided. The semiconductor device may include a first two-dimensional material layer including a first two-dimensional semiconductor material; a plurality of second two-dimensional material layers connected to the first two-dimensional material layer, each having a thickness greater than that of the first two-dimensional material layer, and including a doped two-dimensional semiconductor material; and a plurality of electrodes on the plurality of second two-dimensional material layers.
    Type: Grant
    Filed: January 16, 2023
    Date of Patent: September 1, 2026
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Junyoung Kwon, Sangwoo Kim, Kyung-Eun Byun, Minsu Seol, Minseok Shin, Pin Zhao, Taehyeong Kim, Jaehwan Jung
  • Publication number: 20260239657
    Abstract: Provided are a semiconductor device including a two-dimensional (2D) material, a method of manufacturing the semiconductor device, and an electronic device including the semiconductor device. The semiconductor device includes at least one channel layer including a two-dimensional (2D) semiconductor material, a source electrode and a drain electrode, provided on both sides of each channel layer of the at least one channel layer, and a gate electrode provided on each channel layer of the at least one channel layer, between the source electrode and the drain electrode. Each channel layer of the at least one channel layer includes a source region contacting the source electrode, and a drain region contacting the drain electrode, and at least one of the source region and the drain region includes a metallic grain boundary.
    Type: Application
    Filed: January 30, 2026
    Publication date: August 13, 2026
    Applicants: Samsung Electronics Co., Ltd., President and Fellows Of Harvard College
    Inventors: Changhyun KIM, Elise BRUTSCHEA, Hongkun PARK, Bingchen DENG, Minsu SEOL, Kyung-Eun BYUN, Yeonchoo CHO
  • Patent number: 12684823
    Abstract: Provided are a layer structure including a configuration capable of increasing the operation characteristics of a device including the layer structure, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure includes a first layer and a second layer on one surface of the first layer and facing the first layer. The first layer and the second layer overlap each other. One layer of the first layer and the second layer has a trace of applied strain, and an other layer of the first layer and the second layer is a strain-inducing layer that applies a strain to the one layer.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: July 14, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minsu Seol, Junyoung Kwon, Minseok Yoo
  • Patent number: 12672320
    Abstract: Provided are a complex of heterogeneous two-dimensional materials and a method of manufacturing the same. The complex of heterogeneous two-dimensional materials may include a substrate; a first two-dimensional material layer on the substrate and having a two-dimensional crystal structure; and a second two-dimensional material layer between the substrate and the first two-dimensional material layer. The second two-dimensional material layer have a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded to each other.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: June 30, 2026
    Assignees: Samsung Electronics Co., Ltd., UNIST (ULSAN NATIONAL INSTITUTE OF SCIENCE AND TECHNOLOGY)
    Inventors: Minsu Seol, Hyeonsuk Shin, Kyung-Eun Byun, Hyuntae Hwang, Changseok Lee, Hyeongjoon Kim
  • Patent number: 12666661
    Abstract: A semiconductor device includes a substrate including a gate electrode therein, a trench penetrating the gate electrode and arranged in the substrate, a gate insulating layer in the trench and an upper surface of the substrate, a channel layer on the gate insulating layer and including a two-dimensional (2D) semiconductor material, and a source electrode and a drain electrode, which are spaced apart from each other on the channel layer.
    Type: Grant
    Filed: January 12, 2023
    Date of Patent: June 23, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junyoung Kwon, Minsu Seol, Keunwook Shin, Minseok Yoo
  • Publication number: 20260143736
    Abstract: Provided are a semiconductor device including a two-dimensional nano-crystalline grain channel, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. The semiconductor device includes a channel layer, a gate electrode disposed to face the channel layer, a gate insulating film disposed between the channel layer and the gate electrode, and a source electrode and a drain electrode electrically connected to the channel layer. The channel layer includes a first transition metal dichalcogenide layer and a second transition metal dichalcogenide layer disposed on the first transition metal dichalcogenide layer. The first transition metal dichalcogenide layer includes a highly crystalline transition metal dichalcogenide material having a two-dimensional crystal structure. The second transition metal dichalcogenide layer includes a nano-crystalline grain transition metal dichalcogenide material having a two-dimensional crystal structure.
    Type: Application
    Filed: September 24, 2025
    Publication date: May 21, 2026
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Minseok YOO, Minsu SEOL, Alum JUNG
  • Patent number: 12635204
    Abstract: A semiconductor device includes a channel including a two-dimensional (2D) semiconductor material, a source electrode and a drain electrode electrically connected to opposite sides of the channel, respectively, a transition metal oxide layer on the channel and including a transition metal oxide, a dielectric layer on the transition metal oxide layer and including a high-k material, and a gate electrode on the dielectric layer.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: May 19, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Changhyun Kim, Minsu Seol, Junyoung Kwon, Keunwook Shin, Minseok Yoo
  • Publication number: 20260020278
    Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device may include a source electrode, a drain electrode, an insulating region between the source electrode and the drain electrode, and a channel layer. The channel layer may be on the source electrode, the insulating region, and the drain electrode. The channel layer may include a source region on the source electrode, a drain region on the drain electrode, and a channel region on the insulating region. The source region and the drain region may include a precious metal element. The precious metal element in the drain region may be the same as the precious metal element in the source region. The channel region may include a first two-dimensional material layer having precious metal element-based semiconductor characteristics that may be the same as precious metal element-based semiconductor characteristics of the precious metal element.
    Type: Application
    Filed: July 9, 2025
    Publication date: January 15, 2026
    Applicants: Samsung Electronics Co., Ltd., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Minseok YOO, Kibum KANG, Minseung GYEON, Minsu SEOL
  • Publication number: 20250338574
    Abstract: An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.
    Type: Application
    Filed: July 10, 2025
    Publication date: October 30, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Junyoung KWON, Minsu SEOL, Hyeonjin SHIN, Minseok YOO
  • Publication number: 20250318172
    Abstract: A semiconductor device may include a channel layer including a two-dimensional material layer and a molecular crystal layer on the two-dimensional material layer, the two-dimensional material layer including a two-dimensional semiconductor material; a source electrode and a drain electrode, which respectively may be on both sides of the channel layer; and a gate insulating layer and a gate electrode, which respectively may be on the channel layer between the source electrode and the drain electrode. The molecular crystal layer may include a plate-shaped aromatic compound of C20-C40, and may have a thickness of 1 molecular layer to 5 molecular layers.
    Type: Application
    Filed: April 7, 2025
    Publication date: October 9, 2025
    Applicants: Samsung Electronics Co., Ltd., THE UNIVERSITY OF CHICAGO
    Inventors: Minsu SEOL, Junyoung KWON, Huije RYU, Tomojit CHOWDHURY, Jiwoong PARK, Ce LIANG, Fauzia MUJID
  • Publication number: 20250280590
    Abstract: Disclosed are an electronic device including a two-dimensional material, and a method of fabricating the electronic device. The electronic device may include a first metal layer including a transition metal, a second metal layer on the first metal layer and including gold (Au), and a two-dimensional material layer between the first metal layer and the second metal layer. The two-dimensional material layer may include a transition metal dichalcogenide (TMD). The two-dimensional material layer may be formed as a chalcogen element diffuses into the second metal layer and reacts with the transition metal of the first metal layer adjacent to the second metal layer.
    Type: Application
    Filed: May 13, 2025
    Publication date: September 4, 2025
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Minseok YOO, Minsu SEOL, Junyoung KWON, Kyung-Eun BYUN, Hyeonjin SHIN, Van Luan NGUYEN
  • Patent number: 12408399
    Abstract: Provided is a semiconductor device which use a two-dimensional semiconductor material as a channel layer. The semiconductor device includes: a gate electrode on a substrate; a gate dielectric on the gate electrode; a channel layer on the gate dielectric; and a source electrode and a drain electrode that may be electrically connected to the channel layer. The gate dielectric has a shape with a height greater than a width, and the channel layer includes a two-dimensional semiconductor material.
    Type: Grant
    Filed: July 2, 2024
    Date of Patent: September 2, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minhyun Lee, Minsu Seol, Yeonchoo Cho, Hyeonjin Shin
  • Patent number: 12402374
    Abstract: An electronic device including a two-dimensional material is provided. The electronic device may include a substrate; a metal layer on a partial region of the substrate; a two-dimensional material layer over the metal layer and an upper surface of the substrate; and an insertion layer between the metal layer and the two-dimensional material layer.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: August 26, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junyoung Kwon, Minsu Seol, Hyeonjin Shin, Minseok Yoo
  • Patent number: 12356668
    Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.
    Type: Grant
    Filed: February 14, 2024
    Date of Patent: July 8, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minsu Seol, Minhyun Lee, Junyoung Kwon, Hyeonjin Shin, Minseok Yoo
  • Publication number: 20250220928
    Abstract: A semiconductor device includes a first semiconductor chip that includes a semiconductor substrate which includes a plurality of circuit elements and a wiring structure which is disposed on the semiconductor substrate, and the wiring structure includes a plurality of wiring layers and one or more power gating elements disposed in the plurality of wiring layers, and the power gating elements are transistors including channel portions, gate electrodes, source electrodes, and drain electrodes, and the channel portions include a two-dimensional semiconductor material.
    Type: Application
    Filed: August 27, 2024
    Publication date: July 3, 2025
    Inventors: Chang Seok LEE, Sangwon KIM, Joonseok KIM, Minsu SEOL
  • Patent number: 12341063
    Abstract: Disclosed are an interconnect structure, an electronic device including the same, and a method of manufacturing the interconnect structure. The interconnect structure includes a dielectric layer; a conductive interconnect on the dielectric layer; and a graphene cap layer on the conductive interconnect. The graphene cap layer contains graphene quantum dots, has a carbon content of 80 at % or more, and has an oxygen content of 15 at % or less.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: June 24, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keunwook Shin, Minsu Seol, Sangwon Kim, Kyung-Eun Byun, Hyeonjin Shin
  • Patent number: 12334357
    Abstract: A method of forming a material film includes providing a non-photosensitive mask on a substrate to expose a partial region of the substrate, forming a material film on the partial region of the substrate using a sputtering process, removing the non-photosensitive mask, and heat-treating the substrate and the material film from which the non-photosensitive mask is removed under a first gas atmosphere. The material film includes a transition metal and a chalcogen element. The sputtering process may include an RF magnetron sputtering process. The heat treatment may be performed at a higher temperature than a temperature of the forming the material film.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: June 17, 2025
    Assignees: Samsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
    Inventors: Kyung-Eun Byun, Sangwoo Kim, Minsu Seol, Hyeonjin Shin, Minseok Shin, Pin Zhao, Taehyeong Kim, Jaehwan Jung
  • Patent number: 12336259
    Abstract: Disclosed are an electronic device including a two-dimensional material, and a method of fabricating the electronic device. The electronic device may include a first metal layer including a transition metal, a second metal layer on the first metal layer and including gold (Au), and a two-dimensional material layer between the first metal layer and the second metal layer. The two-dimensional material layer may include a transition metal dichalcogenide (TMD). The two-dimensional material layer may be formed as a chalcogen element diffuses into the second metal layer and reacts with the transition metal of the first metal layer adjacent to the second metal layer.
    Type: Grant
    Filed: December 8, 2021
    Date of Patent: June 17, 2025
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minseok Yoo, Minsu Seol, Junyoung Kwon, Kyung-Eun Byun, Hyeonjin Shin, Van Luan Nguyen