Abstract: An image sensor may include a substrate and a plurality of pixel regions. At least one of the plurality of pixel regions includes a photoelectric conversion portion in the substrate and a pixel circuit adjacent to the first surface of the substrate. The pixel circuit may include a plurality of buried patterns, which each may have a buried structure in the substrate. The pixel circuit may include a first transistor including a first gate electrode and a second transistor including a second gate electrode. The first gate electrode may be a vertical transfer gate electrode. A cross-sectional shape of the second gate electrode may be different from a cross-sectional shape of the first gate electrode. The plurality of buried patterns may include the first gate electrode and the second gate electrode.

Abstract: An image sensor that includes a substrate region including first and second pixel regions; and a microlens array layer on the substrate region and including a first microlens and a second microlens respectively corresponding to the first and second pixel regions. The first pixel region and the second pixel region are respectively adjacent to a center and an edge of the microlens array layer. The first microlens is offset from the first pixel region and has a first inclination. The second microlens is offset from the second pixel region and has a second inclination greater than the first inclination. A degree to which the first and second microlenses are offset from the first and second pixel regions, and the first and second inclinations are based on an incident angle of incident light to the first and second microlenses.

Abstract: A low temperature method of fabrication of short-wave infrared (SWIR) detector focal plane arrays is based on a first series of process steps realizing a CMOS processed readout wafer. A slightly doped buffer layer is transferred on the readout wafer, the slightly doped buffer layer including an interface layer, in contact with the readout wafer, is crystallized, by annealing, at temperatures compatible with the CMOS processed readout wafer, by applying short light source pulses on the interface layer to achieve a high quality crystalline interface layer. The method assures a temperature profile between the light entrance surface of the slightly doped buffer layer and the readout electronics so the annealing temperature remains compatible with the CMOS structure. The slightly doped buffer layer is then used for further grow, on top of it, a GeSn or SiGeSn layer to create a SWIR light conversion layer, achieving the final structure.