Patents by Inventor Minto Zheng

Minto Zheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • STAGGERED DUAL-SIDE MULTI-CHIP INTERCONNECT
    Publication number: 20230411365
    Abstract: Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.
    Type: Application
    Filed: September 6, 2023
    Publication date: December 21, 2023
    Applicant: NVIDIA Corp.
    Inventors: Shuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma
  • Staggered dual-side multi-chip interconnect
    Patent number: 11798923
    Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: October 24, 2023
    Assignee: NVIDIA CORP.
    Inventors: Shuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma
  • Staggered Dual-Side Multi-Chip Interconnect
    Publication number: 20230197696
    Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.
    Type: Application
    Filed: December 16, 2021
    Publication date: June 22, 2023
    Applicant: NVIDIA Corp.
    Inventors: Shuo Zhang, Eric Zhu, Minto Zheng, Michael Zhai, Town Zhang, Jie Ma
  • Semiconductor assembly
    Patent number: 11616019
    Abstract: A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 28, 2023
    Assignee: NVIDIA Corp.
    Inventors: Jacky Qiu, Martin Ding, Jerry Zhou, Minto Zheng
  • Semiconductor Assembly
    Publication number: 20220199528
    Abstract: A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Jacky Qiu, Martin Ding, Jerry Zhou, Minto Zheng