Abstract: A method of manufacturing a CMOS image sensor includes providing a semiconductor substrate having a front side and a back side, forming at least two pixels in the front side, forming a shallow trench isolation in the front side between the at least two pixels, forming a deep trench in the back side at a location above the shallow trench isolation, and depositing a dielectric layer in the deep trench to form a crosstalk reduction element.

Abstract: A method of manufacturing a CMOS image sensor includes providing a semiconductor substrate having a front side and a back side, forming at least two pixels in the front side, forming a shallow trench isolation in the front side between the at least two pixels, forming a deep trench in the back side at a location above the shallow trench isolation, and depositing a dielectric layer in the deep trench to form a crosstalk reduction element.

Abstract: A CMOS image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes a semiconductor substrate having a front side and a back side, at least two pixels disposed in the first side, a shallow trench isolation disposed in the front side between the at least two pixels, and a crosstalk reduction element disposed in the back side at a location above the shallow trench isolation. The crosstalk reduction element reduces optical and electrical crosstalk and improves the image quality of the CMOS image sensor.

Abstract: A CMOS image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes a semiconductor substrate having a front side and a back side, at least two pixels disposed in the first side, a shallow trench isolation disposed in the front side between the at least two pixels, and a crosstalk reduction element disposed in the back side at a location above the shallow trench isolation. The crosstalk reduction element reduces optical and electrical crosstalk and improves the image quality of the CMOS image sensor.

Abstract: A semiconductor device includes a first substrate and a second substrate being bonded to each other, a posterior interconnect layer interposed between the first and second substrates, a weld pad disposed in the posterior interconnect layer, and a first annular opening disposed in the first substrate. The device further includes a dielectric layer formed in the first opening, a via surrounded by the first annular opening, and an interconnect layer disposed in the via. The device also includes a conductive bump disposed on the interconnect layer and electrically connected to the weld pad through the interconnect layer.

Abstract: A semiconductor device includes a first substrate and a second substrate being bonded to each other, a posterior interconnect layer interposed between the first and second substrates, a weld pad disposed in the posterior interconnect layer, and a first annular opening disposed in the first substrate. The device further includes a dielectric layer formed in the first opening, a via surrounded by the first annular opening, and an interconnect layer disposed in the via. The device also includes a conductive bump disposed on the interconnect layer and electrically connected to the weld pad through the interconnect layer.