Abstract: A transmission system for converting a signal of a 9-channel encoder into a 1000 Mbps PHY signal, includes a PHY chip circuits U1 and U2, digital photocouplers U3˜U11, 485 transceivers U12˜U20, RJ45 isolation transformer-integrated jacks J1 and J2, a field programmable gate array (FPGA) chip circuit, an electronic propulsion control system (EPCS) configuration chip circuit, a Jtag interface and SM-6P-PCB jackets J3˜J11, wherein two-channel MII digital signal output and input ends of the FPGA chip circuit are respectively connected with MII digital signal input and output ends of the PHY chip circuits U1 and U2; differential data signal output and input ends of the PHY chip circuits U1 and U2 are respectively connected to the RJ45 isolation transformer-integrated jacks J1 and J2, and a master station and a slave station are arranged at the same time.

Abstract: A transmission system for converting a signal of a 9-channel encoder into a 1000 Mbps PHY signal, includes a PHY chip circuits U1 and U2, digital photocouplers U3˜U11, 485 transceivers U12˜U20, RJ45 isolation transformer-integrated jacks J1 and J2, a field programmable gate array (FPCiA) chip circuit, an electronic propulsion control system (EPCS) configuration chip circuit, a Jtag interface and SM-6P-PCB jackets J3˜J11, wherein two-channel MII digital signal output and input ends of the FPGA chip circuit are respectively connected with MII digital signal input and output ends of the PHY chip circuits U1 and U2; differential data signal output and input ends of the PHY chip circuits U1 and U2 are respectively connected to the RJ45 isolation transformer-integrated jacks J1 and J2, and a master station and a slave station are arranged at the same time.