Abstract: An apparatus includes a processor that monitors a first operational status of processors, activates one of unactivated processors of the processors, and based on a second operational status of the activated processor, determines an activation timing of a next processor to activate next, and activates the next processor at the activation timing.

Abstract: A packet control method implemented by a processor provided in a transmission apparatus including a buffer, the method includes sequentially writing a plurality of packets which are received, to a plurality of regions in the buffer, when sequentially receiving the plurality of packets; acquiring time information indicating a time when each of the plurality of packets is written to one of the plurality of regions, for each packet; sequentially reading the plurality of packets from the plurality of regions; determining an order to write a plurality of new packets to the plurality of regions, based on the time information of each of the plurality of packets which are read; and writing the plurality of new packets to the plurality of regions, according to the determined order, when sequentially receiving the plurality of new packets.