Patents by Inventor Miodrag Temerinac

Miodrag Temerinac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6215830
    Abstract: A carrier control loop (1) for a receiver of digitally transmitted signals is disclosed comprising, in the direction of signal flow, a quadrature demodulator (3), a symbol recognition device (4), a detector (9) for forming a phase deviation value (&phgr;d) and/or a frequency deviation value (fd), a feedback device (10), and a variable-frequency oscillator (11) connected to the quadrature demodulator (3). An evaluating device (12) determines from signals (I, Q) of the carrier control loop (1) a reliability value (z) for the measured phase deviation value (&phgr;d) and/or frequency deviation value (fd), and controls the carrier control loop (1) in accordance with the determined reliability value.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: April 10, 2001
    Assignee: Micronas GmbH
    Inventors: Miodrag Temerinac, Franz-Otto Witte
  • Patent number: 6141646
    Abstract: A digital sound processor for processing multiple standard sound signals and including an audio source which is connected to a digital control input of the sound processor and generates, via externally or internally applied control signals, an audible signal or an audible signal sequence which is fed via the output devices of the sound processor to reproducers.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: October 31, 2000
    Assignee: Micronas Intermetall GmbH
    Inventors: Martin Winterer, Miodrag Temerinac
  • Patent number: 5887036
    Abstract: A logical block is disclosed for decoding a data sequence encoded by a convolutional code, in which a given number of states are to be evaluated. These given states are assigned the given number of state memories which store an associated path and an accumulated distance value. The given number of state memories are associated with parallel processing blocks which each have, as the smallest group to be processed in parallel, two state memories to be read from first and second parallel processing blocks, and two state memories to be written into third and fourth parallel processing blocks. Optimum memory organization permits simple parallel processing and reduction in circuit complexity.
    Type: Grant
    Filed: October 3, 1996
    Date of Patent: March 23, 1999
    Assignee: Deutsche ITT Industries GmbH
    Inventor: Miodrag Temerinac
  • Patent number: 5717618
    Abstract: An improved method for digital interpolation of signals for a second interpolation filter is disclosed which permits a high signal/noise ratio with a minimum amount of circuitry for an overall system comprising first and second interpolation filters. The method for digital interpolation of signals requires multiplying delayed input values locked to a first signal by corresponding weighting factors which are dependent on a time-difference value determined by the interpolating instant and the time grid of the first clock signal. The weighting factors are determined by an impulse response in the time domain. The associated transfer function has an attenuation characteristic in the frequency domain which, with respect to the stop bands, is limited essentially to the alias regions located at the frequency multiples of the first clock signal.
    Type: Grant
    Filed: July 31, 1995
    Date of Patent: February 10, 1998
    Assignee: Deutsche ITT Industries GmbH
    Inventors: Andreas Menkhoff, Miodrag Temerinac, Franz-Otto Witte, Martin Winterer