Abstract: An adjustable oscillator for dynamically optimizing a damping coefficient of a PLL circuit including a gain controlled oscillator circuit and a damping controller. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals and generates a third clock signal which has a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator circuit has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator circuit. The damping controller adjusts gain of the oscillator circuit in response to changes of the clock multiplier to minimize variation of the damping coefficient.

Abstract: A damping coefficient variation mechanism for a PLL including a bias controller, a gain control circuit, and an oscillator circuit. The PLL receives an input clock signal and provides an output clock at a frequency that is the frequency of the input clock multiplied by a clock multiplier. The bias controller has an input receiving a loop control signal and an output providing one or more bias signals. The gain control circuit has bias inputs receiving the bias signals, a gain control input receiving a gain control value, and an output providing a control signal. The oscillator circuit has an input receiving the control signal and an output providing the output clock signal. The gain control circuit provides the control signal to adjust frequency of the output clock signal based on the loop control signal at a gain determined by the gain control value.

Abstract: A damping coefficient correction mechanism for a PLL circuit including a gain controlled oscillator circuit, a damping controller, and gain compensation logic. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals for generating a third clock signal having a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator. The damping controller adjusts gain of the oscillator in response to changes of the clock multiplier. The gain compensation logic is programmable and adjusts the gain control signal.

Abstract: A complementary input dynamic logic circuit for evaluating a logic function including an N-channel dynamic circuit, a P-channel dynamic circuit and a pass device. The N-channel dynamic circuit determines a complement of the logic function when a clock signal is high by pulling a first evaluation node low if it evaluates. The P-channel dynamic circuit also determines a complement of the logic function when the clock signal is high by pulling a second evaluation node high if the P-channel dynamic circuit evaluates. The pass device is controlled by the first evaluation node and pulls the second evaluation node low if the N-channel dynamic circuit fails to evaluate. An inverted version of the clock signal may be used to drive the second evaluation node low through the pass device. The N- and P-channel dynamic circuits may be implemented with parallel-coupled devices to achieve high fan-in implementations.

Abstract: A muxed-decoder circuit including multiple complementary input dynamic circuits and an AND logic gate. Each complementary input dynamic circuit includes a complementary P-logic AND dynamic circuit, a complementary N-logic AND dynamic circuit and a pass device. The complementary P-logic AND dynamic circuit has an output coupled to a corresponding output evaluation node, and evaluates bits of an encoded address value corresponding and bits of a digital select value having a logic state for selecting the encoded address. The complementary N-logic AND dynamic circuit has an output coupled to a corresponding preliminary evaluation node, and evaluates inverted bits of the address value and the digital select value. The pass device is coupled between corresponding first and second evaluation nodes and drives the second evaluation node low if the complementary N-logic AND dynamic circuit fails to evaluate. The AND logic gate couples to the output evaluation nodes and provides a corresponding decoded bit.

Abstract: A complementary input dynamic logic circuit for evaluating a complex logic function including complementary input dynamic logic circuits, P-channel devices, an inverter/driver for providing an inverted clock signal, and N-channel pass devices. Each complementary input dynamic logic circuit determines a complementary AND function for a corresponding one of multiple sets of AND terms and indicates the complementary AND function via a corresponding one of multiple preliminary evaluation nodes. The P-channel devices are coupled in series between a source voltage and an output evaluation node. Each series-coupled P-channel device has a gate coupled to a corresponding preliminary evaluation node. The N-channel pass devices are coupled in parallel between the output evaluation node and the inverter/driver. Each N-channel pass device has a gate coupled to a corresponding preliminary evaluation node.

Abstract: A muxed-decoder circuit including multiple complementary input dynamic circuits and an AND logic gate. Each complementary input dynamic circuit includes a complementary P-logic AND dynamic circuit, a complementary N-logic AND dynamic circuit and a pass device. The complementary P-logic AND dynamic circuit has an output coupled to a corresponding output evaluation node, and evaluates bits of an encoded address value corresponding and bits of a digital select value having a logic state for selecting the encoded address. The complementary N-logic AND dynamic circuit has an output coupled to a corresponding preliminary evaluation node, and evaluates inverted bits of the address value and the digital select value. The pass device is coupled between corresponding first and second evaluation nodes and drives the second evaluation node low if the complementary N-logic AND dynamic circuit fails to evaluate. The AND logic gate couples to the output evaluation nodes and provides a corresponding decoded bit.

Abstract: A complementary input dynamic logic circuit for evaluating a logic function including an N-channel dynamic circuit, a P-channel dynamic circuit and a pass device. The N-channel dynamic circuit determines a complement of the logic function when a clock signal is high by pulling a first evaluation node low if it evaluates. The P-channel dynamic circuit also determines a complement of the logic function when the clock signal is high by pulling a second evaluation node high if the P-channel dynamic circuit evaluates. The pass device is controlled by the first evaluation node and pulls the second evaluation node low if the N-channel dynamic circuit fails to evaluate. An inverted version of the clock signal may be used to drive the second evaluation node low through the pass device. The N- and P-channel dynamic circuits may be implemented with parallel-coupled devices to achieve high fan-in implementations.

Abstract: A complementary input dynamic logic circuit for evaluating a complex logic function including complementary input dynamic logic circuits, P-channel devices, an inverter/driver for providing an inverted clock signal, and N-channel pass devices. Each complementary input dynamic logic circuit determines a complementary AND function for a corresponding one of multiple sets of AND terms and indicates the complementary AND function via a corresponding one of multiple preliminary evaluation nodes. The P-channel devices are coupled in series between a source voltage and an output evaluation node. Each series-coupled P-channel device has a gate coupled to a corresponding preliminary evaluation node. The N-channel pass devices are coupled in parallel between the output evaluation node and the inverter/driver. Each N-channel pass device has a gate coupled to a corresponding preliminary evaluation node.