Abstract: Systems, methods, and apparatus to transition a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.

Abstract: Systems, methods, and apparatus to transition a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.

Abstract: This application relates to systems, methods, and apparatus for transitioning a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.

Abstract: This application relates to systems, methods, and apparatus for transitioning a display device between operating modes using a single dedicated pin of a circuit connected to the display device. The dedicated pin can receive a packet signal corresponding to an operating mode for the display device, and the circuit can thereafter cause the display device to transition into the desired operating mode in response to receiving the packet signal. The operating mode can be a low power on mode where an interface connected to the circuit is deactivated and at least some circuitry of the display device is throttled or powered off. The display device can be driven in an all black state while in the low power on mode, thereby allowing the display device to more quickly transition out of the low power on mode compared to when the display device is completely off.

Abstract: A method for testing integrated circuit-to-substrate joints that electrically connect an IC to a substrate. An ammeter is coupled to a test node of the driver IC, while the test node is coupled to a current source, and a measured current output of the ammeter is recorded. A voltmeter is coupled to the test node while the test node is coupled to an end node of a group of dummy IC-to-substrate joints that are daisy chained; a first measured voltage output of the voltmeter is then recorded. The IC then couples the test node to another end node of the daisy chained dummy joints, and a second measured voltage output is recorded. A resistance or admittance value for the electrical connection of the IC to the substrate is then computed, using the first and second measured voltage outputs and the measured current output. Other embodiments are also described and claimed.

Abstract: Systems and methods for monitoring internal resistance of a display may include supplying the display via a capacitor with a first voltage and a second voltage configured to enable the display to receive touch inputs and display image data, respectively. The method may discharge the capacitor at least three times via a first resistor, a second resistor, and the first resistor and second resistor coupled in parallel with each other. The method may monitor three discharge waveforms that corresponds to when the capacitor discharges from the first voltage to the second voltage via the first resistor, the second resistor, and the first resistor and second resistor coupled in parallel with each other. Based at least in part on the discharge waveforms, the method may determine a chip on glass resistance value and a flex on glass resistance value that correspond to an internal resistance of the display.

Abstract: One embodiment of an apparatus to control and sense a voltage through a single node can include a comparator to monitor single node voltage, a transistor to discharge voltage through the single node and control logic. The control logic can have at least two operational phases when actively controlling the voltage through the single node. In a first phase, the control logic can configure the comparator to determine if the single node voltage is greater than a reference voltage. In a second phase, the control logic can configure the transistor to discharge voltage through the single node when the comparator has previously indicated that the single node voltage is greater than a reference voltage. The control logic can alternatively execute first and second phases to discharge the voltage to a predetermined level.

Abstract: A method for testing integrated circuit-to-substrate joints that electrically connect an IC to a substrate. An ammeter is coupled to a test node of the driver IC, while the test node is coupled to a current source, and a measured current output of the ammeter is recorded. A voltmeter is coupled to the test node while the test node is coupled to an end node of a group of dummy IC-to-substrate joints that are daisy chained; a first measured voltage output of the voltmeter is then recorded. The IC then couples the test node to another end node of the daisy chained dummy joints, and a second measured voltage output is recorded. A resistance or admittance value for the electrical connection of the IC to the substrate is then computed, using the first and second measured voltage outputs and the measured current output. Other embodiments are also described and claimed.

Abstract: Systems and methods for monitoring internal resistance of a display may include supplying the display via a capacitor with a first voltage and a second voltage configured to enable the display to receive touch inputs and display image data, respectively. The method may discharge the capacitor at least three times via a first resistor, a second resistor, and the first resistor and second resistor coupled in parallel with each other. The method may monitor three discharge waveforms that corresponds to when the capacitor discharges from the first voltage to the second voltage via the first resistor, the second resistor, and the first resistor and second resistor coupled in parallel with each other. Based at least in part on the discharge waveforms, the method may determine a chip on glass resistance value and a flex on glass resistance value that correspond to an internal resistance of the display.

Abstract: One embodiment of an apparatus to control and sense a voltage through a single node can include a comparator to monitor single node voltage, a transistor to discharge voltage through the single node and control logic. The control logic can have at least two operational phases when actively controlling the voltage through the single node. In a first phase, the control logic can configure the comparator to determine if the single node voltage is greater than a reference voltage. In a second phase, the control logic can configure the transistor to discharge voltage through the single node when the comparator has previously indicated that the single node voltage is greater than a reference voltage. The control logic can alternatively execute first and second phases to discharge the voltage to a predetermined level.

Abstract: A novel circuit is provided which allows a storage register to load data from another register utilizing a store signal which is asynchronous to the clock signal used to store data in the first register. A novel store circuit is provided which provides a control signal in response to a store signal, which conditionally loads data into the storage register. The contents of the storage register is either maintained or overwritten, depending upon the relationship of the store signal to the clock signal.