Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. To prevent the low-k dielectric from absorbing moisture when exposed to air, exposed portions of the low-k dielectric are covered with spacers. As can be appreciated, this facilitates integration of low-k dielectrics in passivation levels. Low-k dielectrics in passivation levels help lower capacitance on metal lines, thereby reducing RC delay and increasing signal propagation speeds.

Abstract: In one embodiment, an interconnect line on one level of an integrated circuit is electrically coupled to another interconnect line on another level. The two layers of interconnects may be coupled together using a via. To reduce capacitance between the interconnect lines, an air core is formed between them. The air core may be formed by using a chemistry that includes a noble gas fluoride to etch a sacrificial layer between the interconnect layers.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract: In one embodiment, a via structure includes a liner, a barrier layer over the liner, and an aluminum layer over the barrier layer. The barrier layer helps minimize reaction between the aluminum layer and the liner, thus helping minimize void formation in the via. The liner and the barrier layer may be deposited in-situ by ionized metal plasma (IMP) physical vapor deposition (PVD). In one embodiment, the liner comprises titanium, while the barrier layer comprises titanium nitride.

Abstract: In one embodiment, a method of fabricating an integrated circuit includes forming a low-k dielectric layer over metal lines, forming an adhesion layer over the low-k dielectric layer, and forming a capping layer over the adhesion layer. The low-k dielectric may comprise SiLK™ dielectric material, while the capping layer may comprise TEOS. The resulting stack of dielectric materials may be employed in a passivation level to protect the metal lines. For example, a topside layer may be formed over the capping layer.

Abstract: According to one embodiment (100), a method of forming borderless contacts may include forming a composite layer over a first insulating layer (102). A contact hole may be formed through a composite layer and a first insulating layer (104). A conducting layer may then be formed (106), including within a contact hole. Portions of a conducting layer may then be removed with a composite layer as a polish stop (108), and a contact structure may be formed. A first interconnect structure and a second insulating layer may then be formed over a first insulating layer (110 and 112). A borderless contact pattern may then be etched with a composite layer as an etch stop (114).

Abstract: In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.

Abstract: According to one embodiment, verifying a reticle may include patterning an inspected layer (102-2) according to a reticle pattern, depositing a contrast enhancing layer (104-0) on a patterned layer (102-2), and inspecting a reticle patterned formed in the inspected layer (102-2).

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract: In one embodiment, a sacrificial layer is deposited over a base layer. The sacrificial layer is used to define a subsequently formed floating metal structure. The floating metal structure may be anchored into the base layer. Once the floating metal structure is formed, the sacrificial layer surrounding the floating metal structure is etched to create a unity-k dielectric region separating the floating metal structure from the base layer. The unity-k dielectric region also separates the floating metal structure from another floating metal structure. In one embodiment, a noble gas fluoride such as xenon difluoride is used to etch a sacrificial layer of polycrystalline silicon.

Abstract: In one embodiment, a local interconnect layer in an integrated circuit is formed by depositing a first film over an oxide layer and depositing a second film over the first film. The first film may comprise titanium nitride, while the second film may comprise tungsten, for example. The first film and the second film may be deposited in-situ by sputtering. The second film may be etched using the first film as an etch stop, and the first film may be etched using the oxide layer as an etch stop.

Abstract: A method and a system are provided for forming a borderless contact structure. In particular, a method is provided which includes using an inorganic anti-reflective coating layer as an etch stop to form a borderless contact structure. In some embodiments, the method may include patterning an interconnect line above an inorganic layer with anti-reflective properties and depositing an upper interlevel dielectric layer above the interconnect line. A trench may then be etched within the upper interlevel dielectric layer such that a borderless contact structure may be formed in contact with said interconnect line. Consequently, a semiconductor topography is provided, in such an embodiment, which includes an inorganic anti-reflective coating layer arranged below an interconnect line and a contact structure arranged upon the interconnect line. In some embodiments, a width of the contact structure may be greater than a width of the interconnect line.

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.