Patents by Inventor Miranda Ma

Miranda Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230238953
    Abstract: In a method of operating a circuit, at a beginning of a first edge of a driving signal, a first transistor is turned ON to pull, at a first changing rate, a voltage of the driving signal on the first edge from a first voltage toward a second voltage. Then, in response to the voltage of the driving signal on the first edge reaching a threshold voltage between the first voltage and the second voltage, the first transistor is turned OFF and an output circuit is caused to start a second edge of an output signal in response to the first edge of the driving signal. The second edge has a slew rate corresponding to a second changing rate of the voltage of the driving signal on the first edge from the threshold voltage toward the second voltage. The second changing rate is smaller than the first changing rate.
    Type: Application
    Filed: March 30, 2023
    Publication date: July 27, 2023
    Inventors: Zhen TANG, Lei PAN, Miranda MA
  • Patent number: 11695412
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: July 4, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Patent number: 11626872
    Abstract: A circuit includes first to third transistors. The first transistor includes a first terminal coupled to a first voltage, and a second terminal coupled to a connection. The second transistor includes a gate terminal coupled to the gate terminal of the first transistor, a first terminal coupled to a second voltage, and a second terminal coupled to the connection. The third transistor includes a first terminal coupled to the connection, a second terminal coupled to a node between the second terminals of the first and second transistors. The third transistor is controlled to be turned ON at a beginning of a first edge of a driving signal on the connection to pull a voltage of the driving signal on the first edge toward a threshold voltage, and be turned OFF in response to and after the voltage of the driving signal on the first edge reaching the threshold voltage.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 11, 2023
    Assignees: TSMC CHINA COMPANY, LIMITED, TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Zhen Tang, Lei Pan, Miranda Ma
  • Publication number: 20220352886
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 3, 2022
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Patent number: 11424740
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: August 23, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Publication number: 20220164517
    Abstract: A circuit includes a reference node having a reference voltage level, a first node that carries an input signal having a first voltage level or the reference voltage level, a second node that carries a power supply voltage, a voltage regulator including a source follower that outputs a gate signal having a fractional value of the input signal, a first control circuit that selects the higher of the power supply voltage or the gate signal as a first control signal, a second control circuit that selects the higher of the input signal or the first control signal as a second control signal, and first and second transistors coupled in series between the first node and the reference node and configured to receive the first and second control signals.
    Type: Application
    Filed: February 8, 2022
    Publication date: May 26, 2022
    Inventors: Zhen TANG, Lei PAN, Miranda MA
  • Patent number: 11263380
    Abstract: A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: March 1, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Zhen Tang, Lei Pan, Miranda Ma
  • Publication number: 20210391857
    Abstract: A circuit includes first to third transistors. The first transistor includes a first terminal coupled to a first voltage, and a second terminal coupled to a connection. The second transistor includes a gate terminal coupled to the gate terminal of the first transistor, a first terminal coupled to a second voltage, and a second terminal coupled to the connection. The third transistor includes a first terminal coupled to the connection, a second terminal coupled to a node between the second terminals of the first and second transistors. The third transistor is controlled to be turned ON at a beginning of a first edge of a driving signal on the connection to pull a voltage of the driving signal on the first edge toward a threshold voltage, and be turned OFF in response to and after the voltage of the driving signal on the first edge reaching the threshold voltage.
    Type: Application
    Filed: July 8, 2021
    Publication date: December 16, 2021
    Inventors: Zhen TANG, Lei PAN, Miranda MA
  • Publication number: 20210328585
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Application
    Filed: June 30, 2021
    Publication date: October 21, 2021
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Patent number: 11075625
    Abstract: A circuit includes a driver circuit configured to generate a driving signal having a first edge, an output circuit coupled to the driver circuit via a connection to receive the driving signal on the connection, and a compensation circuit coupled to the connection. The output circuit is configured to generate an output signal in response to the driving signal. A second edge of the output signal has a slew rate corresponding to a changing rate of a voltage of the driving signal on the first edge. The compensation circuit is configured to be enabled at a beginning of the first edge to pull the voltage of the driving signal on the first edge toward a threshold voltage. The compensation circuit is further configured to be disabled in response to and after the voltage of the driving signal on the first edge reaching the threshold voltage.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: July 27, 2021
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Miranda Ma, Zhen Tang, Lei Pan
  • Patent number: 11057035
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Publication number: 20200313669
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Application
    Filed: June 17, 2020
    Publication date: October 1, 2020
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Patent number: 10727831
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: July 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Publication number: 20200119730
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 16, 2020
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Publication number: 20200082050
    Abstract: A circuit includes a reference node configured to carry a reference voltage level, a first node configured to carry a signal having a first voltage level or the reference voltage level, a second node configured to carry a power supply voltage having a power supply voltage level in a power-on mode and the reference voltage level in a power-off mode, and a plurality of transistors coupled in series between the first node and the reference node. Each transistor of the plurality of transistors receives a corresponding control signal of a plurality of control signals, and each control signal has a first value based on the power supply voltage in the power-on mode and a second value based on the signal in the power-off mode.
    Type: Application
    Filed: December 31, 2018
    Publication date: March 12, 2020
    Inventors: Zhen TANG, Lei PAN, Miranda MA
  • Patent number: 10511304
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Lei Pan, Zhen Tang, Miranda Ma
  • Publication number: 20190149149
    Abstract: A device comprises, a first power source providing a first voltage, a second power source providing a second voltage less than the first voltage, a first bias voltage source providing a first bias voltage between the first voltage and the second voltage, a second bias voltage source providing a second bias voltage between the first voltage and the second voltage, the second bias voltage greater than or equal to the first bias voltage. The device also includes an output, a pull up network coupled in series between the first power source and the output pad including: a first gate coupled to the bias voltage source; and a second gate coupled to a signal that varies between first bias voltage and first power source. The device includes and a pull down network coupled between the output pad and second power source and including: a third gate coupled to the second bias voltage source; and a fourth gate coupled to a signal that varies between the second power source and the second bias voltage source.
    Type: Application
    Filed: May 1, 2018
    Publication date: May 16, 2019
    Inventors: Lei Pan, Zhen Tang, Miranda Ma