Abstract: A finite state machine circuit can include a plurality of rows of gain cell embedded Dynamic Random Access Memory (GC-eDRAM) cells that can be configured to store state information representing all N states expressed by a finite state machine circuit. A number of eDRAM switch cells can be electrically coupled to the plurality of rows of the GC-eDRAM cells, where the number of eDRAM switch cells can be arranged in an M×M cross-bar array where M is less than N, and the number of eDRAM switch cells can be configured to provide interconnect for all transitions between the all N states expressed by the finite state machine circuit.

Abstract: In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.

Abstract: A multi-threshold flip-flop circuit having an outside feedback is disclosed. The multi-threshold flip-flop circuit comprises a master latch and a slave latch. Coupled between an output of the slave latch and an input of the master latch, a switchable feedback path is utilized to retain logical values of the slave latch during a sleep mode of the flip-flop circuit.

Abstract: A multi-threshold flip-flop circuit having an outside feedback is disclosed. The multi-threshold flip-flop circuit comprises a master latch and a slave latch. Coupled between an output of the slave latch and an input of the master latch, a switchable feedback path is utilized to retain logical values of the slave latch during a sleep mode of the flip-flop circuit.

Abstract: Methods are provided for improving the efficiency of clock gating within low power clock trees. In a first aspect, a correlation level between a plurality of clock gating signals and their corresponding gates which gate a source clock is determined. The clock gating signals and their corresponding gates are combined into a single clock gating signal and a single corresponding gate if a preselected level of correlation exists therebetween. In a second aspect, an area overlap is determined for a plurality of sinks, and one of the gated drovers of the sinks is removed. The sinks of the removed gated driver then are connected to a remaining gated driver driven by a single clock gating signal and a single corresponding gate. In a third aspect, physically proximate sink clusters are rewired to generate a pure clock gating group within each sink cluster if rewiring the clusters increases wiring length by less than a predetermined amount.