Abstract: A null consumption CMOS switch which may be set by nonvolatile programming is formed by a pair of complementary transistors preferably having a common drain and a common gate. The common gate is coupled to the floating gate a programmable and erasable, nonvolatile memory cell. The common gate/floating gate coupling can be a unitary floating gate structure. The floating gate directly drives the ON or OFF states of the two complementary transistors. On an output node of the switch, represented by the common drain of the pair of transistors, a signal present on a source node of one or the other of the two complementary transistors is replicated. The state of charge of the floating gate, imposed by programming or erasing, may be such as to reach advantageously a potential higher than the supply voltage or lower than the ground potential of the circuit. Different embodiments, such as a polarity selection, a path selector, a TRISTATE selector, and a logic gate selector are described.

Abstract: A programmable logic device has an architecture which permits to implement logic functions through loopable multi-levels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks.

Abstract: CMOS logic circuit with one or more inputs has at least a complementary pair of transistors, the N-channel driver transistor having a gate directly connected to an input while the P-channel load transistor having a gate connected to the output of the second one of two inverters connected in cascade, the input of the first inverter being connected to the input of the circuit. Using two signal inverting stages or inverters for mirroring the input signal on the gate of the load P-channel transistor of the circuit pair permits the defining of the triggering threshold of the circuit with great freedom, the obtaining of a greater switching speed and the reduction of power dissipation under stand-by conditions. The invention is particularly suited for HCT circuits.

Abstract: The influence of the resistance of the connection between a terminal of voltage limiting diodes against discharges of electrostatic nature which may hit a pad of an integrated circuit and a respective common potential node of the integrated circuit (supply or ground node) is unsuspectably critical. A resistance of just few ohms may depress the maximum tolerable discharge voltage by several thousands volts and the relationship between such two parameters is hyperbolic. Such a critical resistance may advantageously be reduced by utilizing more levels of metallization purposely connected in parallel and/or by "shifting" the protection diodes near the real (and not virtual) common potential node of the circuit or by utilizing "ring" metallizations over different levels for both the common potential nodes of the circuit.