Patents by Inventor Miriam Menes
Miriam Menes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220045844Abstract: In one embodiment, data communication apparatus includes a network interface for connection to a network and configured to receive a sequence of data packets from a remote device over the network, the sequence including data blocks, ones of the data blocks having block boundaries that are not aligned with payload boundaries of the packets, and packet processing circuitry to cryptographically process the data blocks using a block cipher so as to write corresponding cryptographically processed data blocks to a memory, while holding segments of respective ones of the received data blocks in the memory, such that the packet processing circuitry stores a first segment of a data block of a first packet in the memory until a second packet is received, and then cryptographically processes the first and second segments together so as to write a corresponding cryptographically processed data block to the memory.Type: ApplicationFiled: April 19, 2021Publication date: February 10, 2022Inventors: Miriam Menes, Noam Bloch, Adi Menachem, Idan Burstein, Ariel Shahar, Maxim Fudim
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Publication number: 20210111996Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.Type: ApplicationFiled: December 1, 2020Publication date: April 15, 2021Inventors: Boris Pismenny, Miriam Menes, Idan Burstein, Liran Liss, Noam Bloch, Ariel Shahar
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Patent number: 10789175Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected profile from plural profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected profile for a selected least recently used (LRU) position in the cache.Type: GrantFiled: June 1, 2017Date of Patent: September 29, 2020Assignee: Mellanox Technologies Ltd.Inventors: Gilad Tal, Gil Moran, Miriam Menes, Gil Kopilov, Shlomo Raikin
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Patent number: 10462075Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.Type: GrantFiled: March 28, 2017Date of Patent: October 29, 2019Assignee: Mellanox Technologies, Ltd.Inventors: Freddy Gabbay, Ido Bukshpan, Alon Webman, Miriam Menes, George Elias, Noam Katz Abramovich
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Patent number: 10419329Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.Type: GrantFiled: March 30, 2017Date of Patent: September 17, 2019Assignee: Mellanox Technologies TLV Ltd.Inventors: Lion Levi, George Elias, Oded Wertheim, Amiad Marelli, Miriam Menes, Itamar Rabenstein, Noam Avital, Evyatar Romlet, Ofir Merdler
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Patent number: 10153962Abstract: Communication apparatus includes multiple interfaces connected to a packet data network, and a memory coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a test packet through an ingress interface of the apparatus, to allocate a space in the buffer for storage of a single copy of the test packet, to replicate and transmit sequentially multiple copies of the stored copy of the test packet through a designated egress interface, to receive an indication of a number of copies of the test packet that are to be transmitted, and responsively to the indication, to terminate replication of the test packet and release the allocated space in the buffer.Type: GrantFiled: June 20, 2016Date of Patent: December 11, 2018Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Amiad Marelli, George Elias, Itamar Rabenstein, Miriam Menes, Ido Bukspan
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Publication number: 20180349292Abstract: A computing system comprises one or more cores. Each core comprises a processor and switch with each processor coupled to a communication network among the cores. Also disclosed are techniques for implementing an adaptive last level allocation policy in a last level cache in a multicore system receiving one or more new blocks for allocating for storage in the cache, accessing a selected access profile from plural access profiles that define allocation actions, according to a least recently used type of allocation and based on a cache action, a state bit, and traffic pattern type for the new blocks of data and handling the new block according to the selected access profile for a selected least recently used (LRU) position in the cache.Type: ApplicationFiled: June 1, 2017Publication date: December 6, 2018Inventors: Gilad Tal, Gil Moran, Miriam Menes, Gil Kopilov, Shlomo Raikin
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Publication number: 20180287928Abstract: Communication apparatus includes a plurality of interfaces for receiving and transmitting data packets from and to a network and a memory, which receives and stores context data with respect to multicast groups. Packet processing circuitry establishes reliable connections over the network with the receiving nodes in the multicast groups, and upon receiving from a packet source on the network an incoming unicast packet containing multicast data and containing multicast metadata that identifies a multicast group, sends an acknowledgment of the incoming unicast packet to the packet source, reads the context data from the memory with respect to the identified multicast group, and transmits multiple outgoing unicast packets containing the multicast data via respective egress interfaces to the receiving nodes in the multicast group over the reliable connections.Type: ApplicationFiled: March 30, 2017Publication date: October 4, 2018Inventors: Lion Levi, George Elias, Oded Wertheim, Amiad Marelli, Miriam Menes, Itamar Rabenstein, Noam Avital, Evyatar Romlet, Ofir Merdler
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Publication number: 20170366442Abstract: Communication apparatus includes multiple interfaces connected to a packet data network, and a memory coupled to the interfaces and configured as a buffer to contain packets received through ingress interfaces while awaiting transmission to the network via respective egress interfaces. Packet processing logic is configured, upon receipt of a test packet through an ingress interface of the apparatus, to allocate a space in the buffer for storage of a single copy of the test packet, to replicate and transmit sequentially multiple copies of the stored copy of the test packet through a designated egress interface, to receive an indication of a number of copies of the test packet that are to be transmitted, and responsively to the indication, to terminate replication of the test packet and release the allocated space in the buffer.Type: ApplicationFiled: June 20, 2016Publication date: December 21, 2017Inventors: Amiad Marelli, George Elias, Itamar Rabenstein, Miriam Menes, Ido Bukspan
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Publication number: 20170201468Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.Type: ApplicationFiled: March 28, 2017Publication date: July 13, 2017Inventors: Freddy Gabbay, Ido Bukshpan, Alon Webman, Miriam Menes, George Elias, Noam Katz Abramovich
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Patent number: 9641465Abstract: A switching device includes a plurality of ports and a switching core, which is coupled to transfer data packets between ingress and egress ports. Switching logic maintains a descriptor queue containing respective descriptors corresponding to the data packets that have been received and queued by the ports, and responsively to the respective descriptors, instructs the switching core to transfer the queued data packets between the ports. Port logic, which is associated with each port, is configured, upon receipt of a data packet from the network at the port, to signal the switching logic to place a descriptor corresponding to the data packet in the descriptor queue and, upon identifying the data packet as meeting a predefined criterion, to convey a request to the switching logic, bypassing the descriptor queue, to instruct the switching core to transfer the data packet immediately to an egress port.Type: GrantFiled: August 22, 2013Date of Patent: May 2, 2017Assignee: Mellanox Technologies, LtdInventors: Freddy Gabbay, Ido Bukshpan, Alon Webman, Miriam Menes, George Elias, Noam Katz Abramovich
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Patent number: 9031063Abstract: A method includes receiving in a network element a packet, which includes a delay field that indicates an overall time delay accumulated by the packet until arriving at the network element. Upon receiving the packet, an interim value is substituted in the delay field. The interim value is indicative of a difference between the overall time delay and an arrival time of the packet at the network element. Before sending the packet from the network element, the overall time delay is updated in the delay field based on the interim value and on a departure time at which the packet is to exit the network element. The packet, including the updated overall time delay, is transmitted from the network element.Type: GrantFiled: February 27, 2013Date of Patent: May 12, 2015Assignee: Mellanox Technologies Ltd.Inventors: Miriam Menes, Freddy Gabbay, Zachy Haramaty
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Patent number: 8861347Abstract: A communication apparatus includes a Content-Addressable Memory (CAM) and packet processing circuitry. The packet processing circuitry is configured to store in respective regions of the CAM multiple Access Control Lists (ACLs) that are defined for respective packet types, to classify an input packet to a respective packet type selected from the packet types, to identify a region holding an ACL defined for the selected packet type, and to process the input packet in accordance with the ACL stored in the identified region.Type: GrantFiled: December 4, 2011Date of Patent: October 14, 2014Assignee: Mellanox Technologies Ltd.Inventors: Gil Bloch, Itamar Rabenstein, Miriam Menes, Ido Bukspan
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Publication number: 20140241344Abstract: A method includes receiving in a network element a packet, which includes a delay field that indicates an overall time delay accumulated by the packet until arriving at the network element. Upon receiving the packet, an interim value is substituted in the delay field. The interim value is indicative of a difference between the overall time delay and an arrival time of the packet at the network element. Before sending the packet from the network element, the overall time delay is updated in the delay field based on the interim value and on a departure time at which the packet is to exit the network element. The packet, including the updated overall time delay, is transmitted from the network element.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Miriam Menes, Freddy Gabbay, Zachy Haramaty
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Publication number: 20130142039Abstract: A communication apparatus includes a Content-Addressable Memory (CAM) and packet processing circuitry. The packet processing circuitry is configured to store in respective regions of the CAM multiple Access Control Lists (ACLs) that are defined for respective packet types, to classify an input packet to a respective packet type selected from the packet types, to identify a region holding an ACL defined for the selected packet type, and to process the input packet in accordance with the ACL stored in the identified region.Type: ApplicationFiled: December 4, 2011Publication date: June 6, 2013Applicant: MELLANOX TECHNOLOGIES LTD.Inventors: Gil Bloch, Itamar Rabenstein, Miriam Menes, Ido Bukspan