Patents by Inventor Miriam R. Reshotko
Miriam R. Reshotko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230371233Abstract: Techniques are provided herein for forming multi-tier memory structures with graded characteristics across different tiers. A given memory structure includes memory cells, with a given memory cell having an access device and a storage device. The access device may include, for example, a thin film transistor (TFT) structure, and the storage device may include a capacitor. Certain geometric or material parameters of the memory structures can be altered in a graded fashion across any number of tiers to compensate for process effects that occur when fabricating a given tier, which also affect any lower tiers. This may be done to more closely match the performance of the memory arrays across each of the tiers.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Abhishek Anil Sharma, Travis W. Lajoie, Forough Mahmoudabadi, Shailesh Kumar Madisetti, Van H. Le, Timothy Jen, Cheng Tan, Jisoo Kim, Miriam R. Reshotko, Vishak Venkatraman, Eva Vo, Yue Zhong, Yu-Che Chiu, Moshe Dolejsi, Lorenzo Ferrari, Akash Kannegulla, Deepyanti Taneja, Mark Armstrong, Kamal H. Baloch, Afrin Sultana, Albert B. Chen, Vamsi Evani, Yang Yang, Juan G. Alzate-Vinasco, Fatih Hamzaoglu
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Publication number: 20230369506Abstract: Techniques are provided herein for forming thin film transistor structures having a laterally recessed gate electrode. The gate electrode may be recessed such that it does not extend under one or both conductive contacts of the transistor. Recessing the lateral dimensions of the gate electrode can reduce gate leakage current and parasitic capacitance. According to an example, a given memory structure generally includes memory cells, with each memory cell having an access device and a storage device. According to some such embodiments, the memory cells are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory cell arrays are formed within the interconnect region. Any of the given TFT structures may include a gate electrode that is laterally recessed such that one or more of the contacts are not directly over the gate electrode.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Abhishek Anil Sharma, Miriam R. Reshotko, Van H. Le, Travis W. Lajoie, Mark Armstrong, Cheng Tan, Timothy Jen, Moshe Dolejsi, Deepyanti Taneja
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Publication number: 20230307352Abstract: Techniques are provided herein for forming backend memory structures with airgaps in an interconnect region above semiconductor devices. The airgaps may be provided between conductive features, such as wordlines, to reduce parasitic capacitance. An interconnect region above a plurality of semiconductor devices includes any number of interconnect layers. A first interconnect layer includes first conductive layers (e.g., wordlines) extending in a first direction with airgaps between adjacent first conductive layers. A second interconnect layer over the first interconnect layer includes at least portions of memory cells over corresponding first conductive layers. A third interconnect layer over the second interconnect layer includes a second conductive layer (e.g., bitline) extending in a second direction over one or more of the at least portions of memory cells.Type: ApplicationFiled: March 25, 2022Publication date: September 28, 2023Applicant: Intel CorporationInventors: Miriam R. Reshotko, Van H. Le, Travis W. Lajoie, Abhishek Anil Sharma
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Patent number: 11749560Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.Type: GrantFiled: September 25, 2018Date of Patent: September 5, 2023Assignee: Intel CorporationInventors: Thomas Marieb, Zhiyong Ma, Miriam R. Reshotko, Christopher Jezewski, Flavio Griggio, Rahim Kasim, Nikholas G. Toledo
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Patent number: 11610810Abstract: A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.Type: GrantFiled: December 21, 2018Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Miriam R. Reshotko, Richard E. Schenker, Nafees Kabir
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Publication number: 20220406782Abstract: An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.Type: ApplicationFiled: June 18, 2021Publication date: December 22, 2022Inventors: Abhishek A. Sharma, Albert B. Chen, Wilfred Gomes, Fatih Hamzaoglu, Travis W. Lajoie, Van H. Le, Alekhya Nimmagadda, Miriam R. Reshotko, Hui Jae Yoo
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Patent number: 11444205Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.Type: GrantFiled: September 26, 2018Date of Patent: September 13, 2022Assignee: Intel CorporatiionInventors: Arnab Sen Gupta, Matthew Metz, Benjamin Chu-Kung, Abhishek Sharma, Van H. Le, Miriam R. Reshotko, Christopher J. Jezewski, Ryan Arch, Ande Kitamura, Jack T. Kavalieros, Seung Hoon Sung, Lawrence Wong, Tahir Ghani
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Patent number: 11417775Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.Type: GrantFiled: July 24, 2018Date of Patent: August 16, 2022Assignee: Intel CorporationInventors: Shriram Shivaraman, Van H. Le, Abhishek A. Sharma, Gilbert W. Dewey, Benjamin Chu-Kung, Miriam R. Reshotko, Jack T. Kavalieros, Tahir Ghani
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Publication number: 20200227568Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 29, 2017Publication date: July 16, 2020Inventors: Van H. LE, Abhishek A. SHARMA, Benjamin CHU-KUNG, Gilbert DEWEY, Ravi PILLARISETTY, Miriam R. RESHOTKO, Shriram SHIVARAMAN, Li Huey TAN, Tristan A. TRONIC, Jack T. KAVALIEROS
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Publication number: 20200203212Abstract: A method for fabricating an integrated circuit comprises forming one or more conductive features supported by pillars of a first insulating layer in a first metal layer. One or more vias are formed in a via layer, the one or more vias over and on the first metal layer and in electrical connection with ones of the one or more conductive features. Subsequent to via formation, air gaps are between adjacent ones of the one or more conductive features in the first metal layer to separate the one or more conductive features. A second insulating layer is formed over the one or more conductive features and over the one or more vias, such that the second insulating layer covers the first metal layer and the via layer while bridging over the air gaps, wherein tops the air gaps are substantially coplanar with tops of the one or more conductive features.Type: ApplicationFiled: December 21, 2018Publication date: June 25, 2020Inventors: Miriam R. RESHOTKO, Richard E. SCHENKER, Nafees KABIR
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Patent number: 10665499Abstract: An embodiment includes first, second, and third metal layers; first, second, and third metal lines included in the second metal layer; a layer including airgaps, the first metal layer being between the layer including airgaps and the second metal layer; a first void between the first and second metal lines and a second void between the second and third metal lines; a conformal layer between the first and second metal lines; an additional layer between the first and second metal layers; wherein the first void includes air and the second void includes air; wherein a first axis intersects the first, second, and third metal lines and the first and second voids; wherein a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer; wherein a third axis, orthogonal to the first axis, intersects the second metal line and the additional layer.Type: GrantFiled: June 28, 2018Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Miriam R. Reshotko, Nafees A. Kabir, Manish Chandhok
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Publication number: 20200098657Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a conductive contact stack above the substrate and in contact with the channel layer, and a gate electrode separated from the channel layer by a gate dielectric layer. The conductive contact stack may be a drain electrode or a source electrode. In detail, the conductive contact stack includes at least a metal layer, and at least a metal sealant layer to reduce hydrogen diffused into the channel layer through the conductive contact stack. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Arnab SEN GUPTA, Matthew METZ, Benjamin CHU-KUNG, Abhishek SHARMA, Van H. LE, Miriam R. RESHOTKO, Christopher J. JEZEWSKI, Ryan ARCH, Ande KITAMURA, Jack T. KAVALIEROS, Seung Hoon SUNG, Lawrence WONG, Tahir GHANI
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Publication number: 20200098619Abstract: Techniques are disclosed for providing cladded metal interconnects. Given an interconnect trench, a barrier layer is conformally deposited onto the bottom and sidewalls of the trench. A first layer of a bilayer adhesion liner is selectively deposited on the barrier layer, and a second layer of the bilayer adhesion liner is selectively deposited on the first layer. An interconnect metal is deposited into the trench above the bilayer adhesion liner. Any excess interconnect metal is recessed to get the top surface of the interconnect metal to a proper plane. Recessing the excess interconnect metal may include recessing previously deposited excess adhesion liner and barrier layer materials. The exposed top surface of the interconnect metal in the trench is then capped with the bilayer adhesion liner materials to provide a cladded metal interconnect core. In some embodiments, the adhesion liner is a single layer adhesion liner.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Applicant: INTEL CORPORATIONInventors: Thomas Marieb, Zhiyong Ma, Miriam R. Reshotko, Christopher Jezewski, Flavio Griggio, Rahim Kasim, Nikholas G. Toledo
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Publication number: 20200035839Abstract: Disclosed herein are transistor gate-channel arrangements that may be implemented in nanowire thin film transistors (TFTs) with textured semiconductors, and related methods and devices. An example transistor gate-channel arrangement may include a substrate, a channel material that includes a textured thin film semiconductor material shaped as a nanowire, a gate dielectric that at least partially wraps around the nanowire, and a gate electrode material that wraps around the gate dielectric. Implementing textured thin film semiconductor channel materials shaped as a nanowire and having a gate stack of a gate dielectric and a gate electrode material wrapping around the nanowire advantageously allows realizing gate all-around or bottom-gate transistor architectures for TFTs with textured semiconductor channel materials.Type: ApplicationFiled: July 24, 2018Publication date: January 30, 2020Applicant: Intel CorporationInventors: Shriram Shivaraman, Van H. Le, Abhishek A. Sharma, Gilbert W. Dewey, Benjamin Chu-Kung, Miriam R. Reshotko, Jack T. Kavalieros, Tahir Ghani
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Publication number: 20200006115Abstract: An embodiment includes first, second, and third metal layers; first, second, and third metal lines included in the second metal layer; a layer including airgaps, the first metal layer being between the layer including airgaps and the second metal layer; a first void between the first and second metal lines and a second void between the second and third metal lines; a conformal layer between the first and second metal lines; an additional layer between the first and second metal layers; wherein the first void includes air and the second void includes air; wherein a first axis intersects the first, second, and third metal lines and the first and second voids; wherein a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer; wherein a third axis, orthogonal to the first axis, intersects the second metal line and the additional layer.Type: ApplicationFiled: June 28, 2018Publication date: January 2, 2020Inventors: Miriam R. Reshotko, Nafees A. Kabir, Manish Chandhok
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Patent number: 9182544Abstract: PLC architectures and fabrication techniques for providing electrical and photonic integration of a photonic components with a semiconductor substrate. In the exemplary embodiment, the PLC is to accommodate optical input and/or output (I/O) as well as electrically couple to a microelectronic chip. One or more photonic chip or optical fiber terminal may be coupled to an optical I/O of the PLC. In embodiments the PLC includes a light modulator, photodetector and coupling regions supporting the optical I/O. Spin-on electro-optic polymer (EOP) may be utilized for the modulator while a photodefinable material is employed for a mode expander in the coupling region.Type: GrantFiled: December 21, 2011Date of Patent: November 10, 2015Assignee: Intel CorporationInventors: Mauro J. Kobrinsky, Miriam R. Reshotko, Ibrahim Ban, Bruce A. Block, Peter L. Chang
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Patent number: 8731346Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a substrate, a laser device formed on the substrate, the laser device including an active layer configured to emit light, and a mode-expander waveguide disposed on the substrate and butt-coupled with the active layer to receive and route the light to a waveguide formed on another substrate. Other embodiments may be described and/or claimed.Type: GrantFiled: June 28, 2012Date of Patent: May 20, 2014Assignee: Intel CorporationInventors: Jia-Hung Tseng, Peter L. Chang, Miriam R. Reshotko, Ibrahim Ban, Mauro J. Kobrinsky, Brian Corbett, Roberto Pagano
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Publication number: 20140086523Abstract: EOP-based photonic devices employing coplanar electrodes and in-plane poled chromophores and methods of their manufacture. In an individual EOP-based photonic device, enhanced performance is achieved through in-plane poled chromophores having opposing polarities, enabling, for example, a push-pull optical modulator with reduced operational voltage and switching power relative to a conventional MZ modulator. For a plurality of EOP-based photonic devices, enhanced manufacturability is achieved through a sacrificial interconnect enabling concurrent in-plane poling of many EOP regions disposed on a substrate.Type: ApplicationFiled: September 27, 2012Publication date: March 27, 2014Inventors: Bruce A. BLOCK, Mauro J. KOBRINSKY, Miriam R. RESHOTKO, Shawna M. Liff
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Publication number: 20140003765Abstract: Embodiments of the present disclosure provide optical connection techniques and configurations. In one embodiment, an apparatus includes a substrate, a laser device formed on the substrate, the laser device including an active layer configured to emit light, and a mode-expander waveguide disposed on the substrate and butt-coupled with the active layer to receive and route the light to a waveguide formed on another substrate. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 28, 2012Publication date: January 2, 2014Inventors: Jia-Hung Tseng, Peter L. Chang, Miriam R. Reshotko, Ibrahim Ban, Mauro J. Kobrinsky, Brian Corbett, Roberto Pagano
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Publication number: 20130279845Abstract: PLC architectures and fabrication techniques for providing electrical and photonic integration of a photonic components with a semiconductor substrate. In the exemplary embodiment, the PLC is to accommodate optical input and/or output (I/O) as well as electrically couple to a microelectronic chip. One or more photonic chip or optical fiber terminal may be coupled to an optical I/O of the PLC. In embodiments the PLC includes a light modulator, photodetector and coupling regions supporting the optical I/O. Spin-on electro-optic polymer (EOP) may be utilized for the modulator while a photodefinable material is employed for a mode expander in the coupling region.Type: ApplicationFiled: December 21, 2011Publication date: October 24, 2013Inventors: Mauro J. Kobrinsky, Miriam R. Reshotko, Ibrahim Ban, Bruce A. Block, Peter L. Chang