Patents by Inventor Miriam Reshotko

Miriam Reshotko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200411427
    Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Kevin Lai LIN, Manish CHANDHOK, Miriam RESHOTKO, Christopher JEZEWSKI, Eungnak HAN, Gurpreet SINGH, Sarah ATANASOV, Ian A. YOUNG
  • Publication number: 20200098930
    Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: September 25, 2018
    Publication date: March 26, 2020
    Inventors: Van H. LE, Tahi GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Shriram SHIVARAMAN, Abhishek SHARMA, NAZILA HARATIPOUR
  • Publication number: 20200006138
    Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Kevin LIN, Sudipto NASKAR, Manish CHANDHOK, Miriam RESHOTKO, Rami HOURANI
  • Publication number: 20200006570
    Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Van H. LE, Rajat PAUL, Abhishek SHARMA, Tahir GHANI, Jack KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Justin WEBER, Shriram SHIVARAMAN
  • Publication number: 20190393356
    Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Van H. LE, Seung Hoon SUNG, Benjamin CHU-KUNG, Miriam RESHOTKO, Matthew METZ, Yih WANG, Gilbert DEWEY, Jack KAVALIEROS, Tahir GHANI, Nazila HARATIPOUR, Abhishek SHARMA, Shriram SHIVARAMAN
  • Publication number: 20190378932
    Abstract: Embodiments disclosed herein include thin film transistors and methods of forming such thin film transistors. In an embodiment, the thin film transistor may comprise a substrate, a gate electrode over the substrate, and a gate dielectric stack over the gate electrode. In an embodiment, the gate dielectric stack may comprise a plurality of layers. In an embodiment, the plurality of layers may comprise an amorphous layer. In an embodiment, the thin film transistor may also comprise a semiconductor layer over the gate dielectric. In an embodiment, the semiconductor layer is a crystalline semiconductor layer. In an embodiment, the thin film transistor may also comprise a source electrode and a drain electrode.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Inventors: Van H. LE, Inanc MERIC, Gilbert DEWEY, Sean MA, Abhishek A. SHARMA, Miriam RESHOTKO, Shriram SHIVARAMAN, Kent MILLARD, Matthew V. METZ, Wilhelm MELITZ, Benjamin CHU-KUNG, Jack KAVALIEROS
  • Publication number: 20190304894
    Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 3, 2019
    Inventors: Vincent DORGAN, Jeffrey HICKS, Miriam RESHOTKO, Abhishek SHARMA, Ilan TSAMERET
  • Patent number: 7948010
    Abstract: Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed layer and a buffer layer. The seed layer of a first material is formed on an insulating layer over a substrate. The buffer layer is formed on the seed layer. Next, an optical layer of a second material is formed on the buffer layer. The buffer layer includes the first material and the second material. In one embodiment, the first material is silicon. In one embodiment, the second material is germanium.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: May 24, 2011
    Assignee: Intel Corporation
    Inventors: Miriam Reshotko, Been-Yih Jin
  • Patent number: 7700975
    Abstract: Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) layer deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. In one embodiment, the semiconductor layer is an intrinsic semiconductor layer. In one embodiment, the thickness of the delta doped layer is less than 100 nanometers. In one embodiment, the delta doped layer has a dopant concentration of at least 1×1018 cm?3. A delta doped layer is formed on portions of a semiconductor layer over a substrate. Metal contacts are formed on the delta doped layer. A buffer layer may be formed between the substrate and the semiconductor layer. In one embodiment, the substrate includes silicon, and the semiconductor layer includes germanium.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: April 20, 2010
    Assignee: Intel Corporation
    Inventors: Titash Rakshit, Miriam Reshotko
  • Publication number: 20090243023
    Abstract: Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed layer and a buffer layer. The seed layer of a first material is formed on an insulating layer over a substrate. The buffer layer is formed on the seed layer. Next, an optical layer of a second material is formed on the buffer layer. The buffer layer includes the first material and the second material. In one embodiment, the first material is silicon. In one embodiment, the second material is germanium.
    Type: Application
    Filed: June 15, 2009
    Publication date: October 1, 2009
    Inventors: Miriam Reshotko, Been-Yih Jin
  • Patent number: 7553687
    Abstract: Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed layer and a buffer layer. The seed layer of a first material is formed on an insulating layer over a substrate. The buffer layer is formed on the seed layer. Next, an optical layer of a second material is formed on the buffer layer. The buffer layer includes the first material and the second material. In one embodiment, the first material is silicon. In one embodiment, the second material is germanium.
    Type: Grant
    Filed: June 28, 2006
    Date of Patent: June 30, 2009
    Assignee: Intel Corporation
    Inventors: Miriam Reshotko, Been-Yih Jin
  • Publication number: 20080014669
    Abstract: Dual seed semiconductor photodetectors and methods to fabricate thereof are described. A dual seed semiconductor photodetector is formed directly on an insulating layer on a substrate. The dual seed semiconductor photodetector includes an optical layer formed on a dual seed semiconductor layer. The dual seed semiconductor layer includes a seed layer and a buffer layer. The seed layer of a first material is formed on an insulating layer over a substrate. The buffer layer is formed on the seed layer. Next, an optical layer of a second material is formed on the buffer layer. The buffer layer includes the first material and the second material. In one embodiment, the first material is silicon. In one embodiment, the second material is germanium.
    Type: Application
    Filed: June 28, 2006
    Publication date: January 17, 2008
    Inventors: Miriam Reshotko, Been-Yih Jin
  • Publication number: 20080001181
    Abstract: Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) regions deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. Band engineering at the metal-semiconductor interfaces using complementarily delta doped semiconductor regions to fix two different interface workfunctions. Delta doping the grounded contact interface with p+ and the reverse biased interface with n+ enhances the Schottky barrier faced by both electrons and holes at the point of injection from source contact into the channel and at the point of collection from the channel into the drain contact.
    Type: Application
    Filed: June 28, 2006
    Publication date: January 3, 2008
    Inventors: Titash Rakshit, Miriam Reshotko
  • Publication number: 20070235877
    Abstract: A semiconductor device is described with a photodetector embedded within and a method of manufacturing the same. The photodetector may be formed above the conductive layers within the device and may detect transmitted light from the top side of the device. The process of manufacturing the device may include a damascene or a subtractive etch process.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 11, 2007
    Inventors: Miriam Reshotko, Bruce Block, David Kencke
  • Publication number: 20070235824
    Abstract: Metal-Semiconductor-Metal (“MSM”) photodetectors and methods to fabricate thereof are described. The MSM photodetector includes a thin heavily doped (“delta doped”) layer deposited at an interface between metal contacts and a semiconductor layer to reduce a dark current of the MSM photodetector. In one embodiment, the semiconductor layer is an intrinsic semiconductor layer. In one embodiment, the thickness of the delta doped layer is less than 100 nanometers. In one embodiment, the delta doped layer has a dopant concentration of at least 1×1018 cm?3. A delta doped layer is formed on portions of a semiconductor layer over a substrate. Metal contacts are formed on the delta doped layer. A buffer layer may be formed between the substrate and the semiconductor layer. In one embodiment, the substrate includes silicon, and the semiconductor layer includes germanium.
    Type: Application
    Filed: March 31, 2006
    Publication date: October 11, 2007
    Inventors: Titash Rakshit, Miriam Reshotko
  • Publication number: 20060263924
    Abstract: A photosensitive device for enabling high speed detection of electromagnetic radiation. The device includes recessed electrodes for providing a generally homogeneous electric field in an active region. Carriers generated in the active region are detected using the recessed electrodes.
    Type: Application
    Filed: July 31, 2006
    Publication date: November 23, 2006
    Inventors: Miriam Reshotko, Shaofeng Yu, Bruce Block
  • Publication number: 20050202312
    Abstract: A photosensitive device for enabling high speed detection of electromagnetic radiation. The device includes recessed electrodes for providing a generally homogeneous electric field in an active region. Carriers generated in the active region are detected using the recessed electrodes.
    Type: Application
    Filed: May 4, 2005
    Publication date: September 15, 2005
    Inventors: Miriam Reshotko, Shaofeng Yu, Bruce Block