Patents by Inventor Miriam Reshotko
Miriam Reshotko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11894270Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.Type: GrantFiled: April 13, 2022Date of Patent: February 6, 2024Assignee: Intel CorporationInventors: Kevin Lin, Sudipto Naskar, Manish Chandhok, Miriam Reshotko, Rami Hourani
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Patent number: 11843054Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.Type: GrantFiled: June 22, 2018Date of Patent: December 12, 2023Assignee: Intel CorporationInventors: Van H. Le, Seung Hoon Sung, Benjamin Chu-Kung, Miriam Reshotko, Matthew Metz, Yih Wang, Gilbert Dewey, Jack Kavalieros, Tahir Ghani, Nazila Haratipour, Abhishek Sharma, Shriram Shivaraman
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Publication number: 20230395506Abstract: Adjacent interconnect features are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within a level of interconnect metallization. Adjacent interconnect features may comprise a plurality of first interconnect lines with spaces therebetween. A dielectric material is over the first interconnect lines and within the spaces between the first interconnect lines. Resultant topography in the dielectric material defines a plurality of trenches between the first interconnect lines. The adjacent interconnect features further comprise a plurality of second interconnect lines interdigitated with the first interconnect lines that occupy at least a portion of the trenches between individual ones of the first interconnect lines.Type: ApplicationFiled: June 6, 2022Publication date: December 7, 2023Applicant: Intel CorporationInventors: Miriam Reshotko, Elijah Karpov, Mark Anders, Gauri Auluck, Shakuntala Sundararajan, Michael Makowski, Caleb Barrett
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Publication number: 20230197601Abstract: Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Jiun-Ruey Chen, Christopher Jezewski, John Plombon, Miriam Reshotko, Mauro Kobrinsky, Scott B. Clendenning
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Publication number: 20230197602Abstract: Adjacent interconnect lines are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within one level of interconnect metallization. Short and tall interconnect via openings are landed on the vertically staggered interconnect lines. Cap material selectively deposited upon upper ones of the staggered interconnect lines limits over etch of the short vias while the tall vias are advanced toward lower ones of the staggered interconnect lines. The via openings of differing depth may be filled, for example with a single damascene metallization process that defines a co-planar top surface for all via metallization over the staggered, vertically spaced interconnect lines.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Elijah Karpov, Miriam Reshotko, Scott B. Clendenning, Jiun-Ruey Chen, Matthew Metz
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Patent number: 11664305Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.Type: GrantFiled: June 27, 2019Date of Patent: May 30, 2023Assignee: Intel CorporationInventors: Kevin Lai Lin, Manish Chandhok, Miriam Reshotko, Christopher Jezewski, Eungnak Han, Gurpreet Singh, Sarah Atanasov, Ian A. Young
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Patent number: 11527656Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.Type: GrantFiled: September 25, 2018Date of Patent: December 13, 2022Assignee: Intel CorporationInventors: Van H. Le, Tahir Ghani, Jack T. Kavalieros, Gilbert Dewey, Matthew Metz, Miriam Reshotko, Benjamin Chu-Kung, Shriram Shivaraman, Abhishek Sharma, Nazila Haratipour
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Publication number: 20220352068Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: ApplicationFiled: June 15, 2022Publication date: November 3, 2022Applicant: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Patent number: 11444024Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: GrantFiled: November 2, 2020Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Publication number: 20220238376Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Inventors: Kevin LIN, Sudipto NASKAR, Manish CHANDHOK, Miriam RESHOTKO, Rami HOURANI
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Patent number: 11335598Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.Type: GrantFiled: June 29, 2018Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Kevin Lin, Sudipto Naskar, Manish Chandhok, Miriam Reshotko, Rami Hourani
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Publication number: 20220139823Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: ApplicationFiled: November 2, 2020Publication date: May 5, 2022Applicant: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Publication number: 20220139772Abstract: Integrated circuit interconnect structures including an interconnect metallization feature with a liner material of a greater thickness between a fill metal and dielectric material, and of a lesser thickness between the fill metal and a lower-level interconnect metallization feature. The liner material may be substantially absent from an interface between the fill metal and the lower-level interconnect metallization feature. Liner material of reduced thickness at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive liner material that may enhance the scalability of interconnect structures. In some embodiments, liner material is deposited upon dielectric surfaces with an area selective atomic layer deposition process. For single damascene implementations, both a via and a metal line may include a selectively deposited liner material.Type: ApplicationFiled: November 2, 2020Publication date: May 5, 2022Applicant: Intel CorporationInventors: Christoper Jezewski, Jiun-Ruey Chen, Miriam Reshotko, James M. Blackwell, Matthew Metz, Che-Yun Lin
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Publication number: 20220102268Abstract: Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Urusa Alaan, Kevin L. Lin, Miriam Reshotko, Sarah Atanasov, Christopher Jezewski, Carl Naylor, Mauro Kobrinsky, Hui Jae Yoo
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Patent number: 11264317Abstract: Embodiments herein may describe techniques for an integrated circuit including a metal interconnect above a substrate, an interlayer dielectric (ILD) layer above the metal interconnect with an opening to expose the metal interconnect at a bottom of the opening. A dielectric layer may conformally cover sidewalls and the bottom of the opening and in contact with the metal interconnect. An electrode may be formed within the opening, above the metal interconnect, and separated from the metal interconnect by the dielectric layer. After a programming voltage may be applied between the metal interconnect and the electrode to generate a current between the metal interconnect and the electrode, a conductive path may be formed through the dielectric layer to couple the metal interconnect and the electrode, changing the resistance between the metal interconnect and the electrode. Other embodiments may be described and/or claimed.Type: GrantFiled: April 2, 2018Date of Patent: March 1, 2022Assignee: Intel CorporationInventors: Vincent Dorgan, Jeffrey Hicks, Miriam Reshotko, Abhishek Sharma, Ilan Tsameret
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Publication number: 20200411427Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.Type: ApplicationFiled: June 27, 2019Publication date: December 31, 2020Inventors: Kevin Lai LIN, Manish CHANDHOK, Miriam RESHOTKO, Christopher JEZEWSKI, Eungnak HAN, Gurpreet SINGH, Sarah ATANASOV, Ian A. YOUNG
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Publication number: 20200098930Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate oriented in a horizontal direction and a transistor above the substrate. The transistor includes a gate electrode above the substrate, a gate dielectric layer around the gate electrode, and a channel layer around the gate dielectric layer, all oriented in a vertical direction substantially orthogonal to the horizontal direction. Furthermore, a source electrode or a drain electrode is above or below the channel layer, separated from the gate electrode, and in contact with a portion of the channel layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 25, 2018Publication date: March 26, 2020Inventors: Van H. LE, Tahi GHANI, Jack T. KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Shriram SHIVARAMAN, Abhishek SHARMA, NAZILA HARATIPOUR
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Publication number: 20200006570Abstract: Embodiments of the present disclosure are contact structures for thin film transistor (TFT) devices. One embodiment is a TFT device comprising: a substrate; a gate formed above the substrate; a TFT channel formed above the substrate; and a pair of contacts formed on the TFT channel, wherein each of the contacts comprises one or more layers including: a metal that is non-reactive with a material of the TFT channel; or a plurality of layers including a first metal layer formed on a second layer, the second layer in contact with the TFT channel and between the first mater layer and the TFT channel. Other embodiments may be disclosed and/or claimed.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Van H. LE, Rajat PAUL, Abhishek SHARMA, Tahir GHANI, Jack KAVALIEROS, Gilbert DEWEY, Matthew METZ, Miriam RESHOTKO, Benjamin CHU-KUNG, Justin WEBER, Shriram SHIVARAMAN
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Publication number: 20200006138Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Kevin LIN, Sudipto NASKAR, Manish CHANDHOK, Miriam RESHOTKO, Rami HOURANI
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Publication number: 20190393356Abstract: Embodiments herein describe techniques for a semiconductor device including a transistor. The transistor includes a first metal contact as a source electrode, a second metal contact as a drain electrode, a channel area between the source electrode and the drain electrode, and a third metal contact aligned with the channel area as a gate electrode. The first metal contact may be located in a first metal layer along a first direction. The second metal contact may be located in a second metal layer along the first direction, in parallel with the first metal contact. The third metal contact may be located in a third metal layer along a second direction substantially orthogonal to the first direction. The third metal layer is between the first metal layer and the second metal layer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 22, 2018Publication date: December 26, 2019Inventors: Van H. LE, Seung Hoon SUNG, Benjamin CHU-KUNG, Miriam RESHOTKO, Matthew METZ, Yih WANG, Gilbert DEWEY, Jack KAVALIEROS, Tahir GHANI, Nazila HARATIPOUR, Abhishek SHARMA, Shriram SHIVARAMAN