Abstract: The system may include a digital-to-analog converter configured to convert a digital signal to an analog signal. The system may include sample/hold circuits configured to receive and store the analog signal. The system may include an address controller configured to regulate which sample/hold circuits propagate the analog signal. The sample/hold circuits may be configured to feed the analog signal to devices of a memory array. The system may include an output circuit configured to program the devices by comparing currents of the devices to a target current. In response to one or more of the currents of the devices being within a threshold range, the output circuit may discontinue programming the corresponding devices. In response to one or more of the currents of the devices not being within the threshold range, the output circuit may continue programming the corresponding devices.

Abstract: A system may include a memory array for VMM and includes a matrix of devices. The devices may be configured to receive a programming signal to program a weight to store a matrix of weights. The devices may be configured to receive a digital signal representative of a vector of input bits. The devices may generate an analog output signal by individually multiplying input bits by a corresponding weight. The system may include multiple ADCs electrically coupled to a corresponding device. Each ADC may be configured to convert a corresponding analog output signal to a digital signal based on a current level of the corresponding analog output signal. The system may include registers electrically coupled to a corresponding ADC configured to shift and store an output vector of bits of a corresponding digital output signal based on an order of the vector of input bits received by the corresponding device.

Abstract: A system for programming memory devices in an array is provided. The system may include a plurality of memory cells that are organized into an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The system may also include a current-compliance circuit that is electrically coupled to one or more memory cells in the plurality of memory cells. The current-compliance circuit may be configured to limit an amount of current supplied to the one or more memory cells during a programming phase of the one or more memory cells.

Abstract: A memory system having a temperature effect compensation mechanism is provided. The memory system may include a plurality of memory cells, where the memory cells are organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The plurality of memory cells may have an operating temperature range. The memory system may also include a temperature-dependent biasing circuit that is configured to reduce a biasing voltage to the plurality of memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increase the biasing voltage to the plurality of memory cells when the temperature of the array is at or near a lower end of the operating temperature range.

Abstract: The system may include a digital-to-analog converter configured to convert a digital signal to an analog signal. The system may include sample/hold circuits configured to receive and store the analog signal. The system may include an address controller configured to regulate which sample/hold circuits propagate the analog signal. The sample/hold circuits may be configured to feed the analog signal to devices of a memory array. The system may include an output circuit configured to program the devices by comparing currents of the devices to a target current. In response to one or more of the currents of the devices being within a threshold range, the output circuit may discontinue programming the corresponding devices. In response to one or more of the currents of the devices not being within the threshold range, the output circuit may continue programming the corresponding devices.

Abstract: Systems and methods with analog to digital converters are provided. The systems and methods may include a plurality of non-volatile memory cells that may be organized into an array. A bitline may be electrically coupled to a column of memory cells vertically arranged in the array. The bitline may be configured to sum up the current produced by the memory cells in the column. A digital-to-analog converter having an output electrically coupled to the bitline may be configured to generate a current and add it through the output to the bitline. A voltage comparator having an input that is electrically coupled to the bitline may be configured to measure a voltage on the bitline and compare it to a fixed voltage, and to stop the digital-to-analog converter from adding current to the bitline when the measured voltage exceeds the fixed voltage.

Abstract: A system for comparing currents is disclosed. The system may include a first current signal and a second current signal. The system may also include a subtractor that is configured to receive a plurality of current input signals and generate a single output current signal that is equal to a difference between the plurality of current input signals. The system may also include a current-to-voltage converter that is configured to receive the output current signal and convert it into an output voltage.

Abstract: A system for programming memory devices in an array is provided. The system may include a plurality of memory cells that are organized into an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The system may also include a current-compliance circuit that is electrically coupled to one or more memory cells in the plurality of memory cells. The current-compliance circuit may be configured to limit an amount of current supplied to the one or more memory cells during a programming phase of the one or more memory cells.

Abstract: A memory system having a temperature effect compensation mechanism is provided. The memory system may include a plurality of memory cells, where the memory cells are organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically. The plurality of memory cells may have an operating temperature range. The memory system may also include a temperature-dependent biasing circuit that is configured to reduce a biasing voltage to the plurality of memory cells when the temperature of the array is at or near an upper end of the operating temperature range and increase the biasing voltage to the plurality of memory cells when the temperature of the array is at or near a lower end of the operating temperature range.

Abstract: Systems and methods with analog to digital converters are provided. The systems and methods may include a plurality of non-volatile memory cells that may be organized into an array. A bitline may be electrically coupled to a column of memory cells vertically arranged in the array. The bitline may be configured to sum up the current produced by the memory cells in the column. A digital-to-analog converter having an output electrically coupled to the bitline may be configured to generate a current and add it through the output to the bitline. A voltage comparator having an input that is electrically coupled to the bitline may be configured to measure a voltage on the bitline and compare it to a fixed voltage, and to stop the digital-to-analog converter from adding current to the bitline when the measured voltage exceeds the fixed voltage.

Abstract: A system for comparing currents is disclosed. The system may include a first current signal and a second current signal. The system may also include a subtractor that is configured to receive a plurality of current input signals and generate a single output current signal that is equal to a difference between the plurality of current input signals. The system may also include a current-to-voltage converter that is configured to receive the output current signal and convert it into an output voltage.

Abstract: The system may include a digital-to-analog converter configured to convert a digital signal to an analog signal. The system may include sample/hold circuits configured to receive and store the analog signal. The system may include an address controller configured to regulate which sample/hold circuits propagate the analog signal. The sample/hold circuits may be configured to feed the analog signal to devices of a memory array. The system may include an output circuit configured to program the devices by comparing currents of the devices to a target current. In response to one or more of the currents of the devices being within a threshold range, the output circuit may discontinue programming the corresponding devices. In response to one or more of the currents of the devices not being within the threshold range, the output circuit may continue programming the corresponding devices.

Abstract: Embodiments related to nonvolatile memory devices each having a charge storage, an activation input, a signal input and signal output to output an output signal when the activation input receives an activation signal. The output signal is in a range that is based on a charge stored in the charge storage, the activation signal applied to the activation input, and the input signal received at the signal input. The nonvolatile memory devices are arranged in a two dimensional (XY) layer that has horizontal rows in a first dimension (X) and vertical columns in a second dimension (Y), the activation inputs of memory devices of each row are connected to a same activation input. The memory devices of the columns have signal inputs connected to signal outputs of memory devices in the row above and have signal outputs connected to the signal inputs of memory devices in the row below.

Abstract: A system may include a memory array for VMM and includes a matrix of devices. The devices may be configured to receive a programming signal to program a weight to store a matrix of weights. The devices may be configured to receive a digital signal representative of a vector of input bits. The devices may generate an analog output signal by individually multiplying input bits by a corresponding weight. The system may include multiple ADCs electrically coupled to a corresponding device. Each ADC may be configured to convert a corresponding analog output signal to a digital signal based on a current level of the corresponding analog output signal. The system may include registers electrically coupled to a corresponding ADC configured to shift and store an output vector of bits of a corresponding digital output signal based on an order of the vector of input bits received by the corresponding device.

Abstract: Systems and methods for a vector-by-matrix multiplier (VMM) module having a three-dimensional memory matrix of nonvolatile memory devices each having a charge storage, an activation input, a signal input and an output signal in a range that is based on a stored charge and an input signal during assertion of the activation signal. The memory devices are arranged in two dimensional (XY) layers that are vertically disposed along (Z) columns. The activation inputs of each layer are connected to a same activation signal, the memory devices of rows in a first dimension (X) of each layer have signal inputs connected to different input signals and have signal outputs connected in series to a common output. The memory devices of rows in a second dimension (Y) of each layer have signal inputs connected to a set of the same inputs along the first dimension.

Abstract: There are disclosed devices, system and methods for a vector-by-matrix multiplier (VMM) module having a three-dimensional memory matrix of nonvolatile memory devices each having a charge storage, an activation input, a signal input and an output signal in a range that is based on a stored charge and an input signal during assertion of the activation signal. The memory devices are arranged in two dimensional (XY) layers that are vertically disposed along (Z) columns. The activation inputs of each layer are connected to a same activation signal, the memory devices of rows in a first dimension (X) of each layer have signal inputs connected to different input signals and have signal outputs connected in series to a common output. The memory devices of rows in a second dimension (Y) of each layer have signal inputs connected to a set of the same inputs along the first dimension.

Abstract: There are disclosed memristors and memristor fabrication methods. A memristor may include a stack of four functional elements including, in sequence, a first electrode, a barrier layer, an oxygen-deficient switching layer, and a second electrode.

Abstract: There are disclosed memristors and memristor fabrication methods. A memristor may include a stack of four functional elements including, in sequence, a first electrode, a barrier layer, an oxygen-deficient switching layer, and a second electrode.

Abstract: A logic gate (1) comprising a spintronic memristor device (2), which has two spin-polarized magnetic electrodes (3, 4) for injecting and/or receiving a spin-polarized current and a layer of material (5) interposed between the two electrodes (3, 4) for transporting the spin-polarized current from one electrode to the other. The layer of material (5) is composed of a layer of organic semiconductor that is able to endow the spintronic memristor device (2) with at least two non-volatile electrical resistance states (RH, RL), each of which can be selected by applying a voltage to the electrodes (3, 4) that reaches or exceeds a respective voltage threshold (VT1, VT2) and, in at least a first resistance state (RH) of which, the spintronic memristor device (2) does not present a magnetoresistive effect.