Abstract: Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided.

Abstract: Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided.

Abstract: A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

Abstract: A memory device is provided including memory cells that are capable of switching between at least two states, where the threshold of a sense signal for detecting the current state depends on a data content of the memory cell. Parallel to a user data block, a primary control word including a predetermined number of bits of a first state is stored in a check section of the cell array. The check section is read by applying sense signals of different amplitudes, where in each case a secondary control word is obtained. By checking in each secondary control word the number of bits of the first state, the margins of the current sense signal amplitude towards the sense window limits may be checked and the sense signal amplitude may be adapted permanently to a sense window drift, so as to enhance the reliability of the memory device.

Abstract: A method for conducting programming and erasure of charge-trapped memory devices includes: conducting at least one program/erase cycle of a charge-trapped memory device on the basis of a given threshold voltage of the charge-trapped memory device as a reference point; determining a wear-level of the erasing procedure; shifting the reference point according to a result of the determination of the wear-level; conducting one or more program/erase cycle on the basis of the shifted threshold; and conducting read and verify operations on the basis of the shifted threshold.

Abstract: A method for setting a read voltage that is used to read data from a nonvolatile memory is disclosed. Logic states from the first state set are stored in a particular number of digits in the multiplicity of memory areas. The memory areas are read in succession. The operation of reading one of the memory areas involves a number of reading steps for reading state information the read voltage being varied for each reading step and the state information that has been read being provided after each reading step. Control information based on the particular number of digits is provided. The state information that has been provided is compared with the control information. The read voltage to be set or a read voltage range to be set is determined on the basis of the results of the comparison.

Abstract: A method, a memory device and a test unit to test such memory device is provided. The memory device comprises a memory cell array including a multitude of memory cells each having a variable characteristic. The method comprises identifying the characteristic of each memory cell and assigning memory cells of the multitude of memory cells to a weak group in dependence on the identified characteristic. Then the stored information of the memory cells assigned to the weak group is restored in order to modify the characteristics of these memory cells.