Abstract: A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.

Abstract: A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.

Abstract: A memory device includes a plurality of data lines, a common source, and control logic. The control logic is configured to implement a seed operation by biasing each of the plurality of data lines to a first voltage level with the common source biased to a second voltage level lower than the first voltage level. With each data line biased to the first voltage level, the control logic is configured to float each data line and bias the common source to the first voltage level such that the bias of each data line is boosted above the first voltage level due to capacitive coupling between each data line and the common source.

Abstract: An oscillator system may include an oscillator block having a plurality of inputs and outputting a clock signal, a frequency divider block receiving the clock signal and outputting a divided clock signal, a tuning block receiving the divided clock signal and outputting a comparison signal, and a control block coupled to the tuning block. The control block may receive the comparison signal. The control block may include a configuration block for producing a plurality of outputs for the corresponding inputs of the oscillator block, and an Up/Down counter having outputs applied to the configuration block.

Abstract: An oscillator system may include an oscillator block having a plurality of inputs and outputting a clock signal, a frequency divider block receiving the clock signal and outputting a divided clock signal, a tuning block receiving the divided clock signal and outputting a comparison signal, and a control block coupled to the tuning block. The control block may receive the comparison signal. The control block may include a configuration block for producing a plurality of outputs for the corresponding inputs of the oscillator block, and an Up/Down counter having outputs applied to the configuration block.