Patents by Inventor Mirlaine Aparecida Crepalde

Mirlaine Aparecida Crepalde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System, method, and computer program product for determining suitability for formal verification
    Patent number: 10956640
    Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include receiving, using a processor, an electronic design and providing at least a portion of the electronic design to a machine learning engine. Embodiments may further include automatically determining, based upon, at least in part, an output of the machine learning engine whether or not the at least a portion of the electronic design is amenable to formal verification.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: March 23, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Georgia Penido Safe, Mirlaine Aparecida Crepalde, Yumi Monma, Felipe Althoff, Fernanda Augusta Braga, Lucas Martins Chaves, Pedro Bruno Neri Silva, Mariana Ferreira Marques, Vincent Gregory Reynolds
  • System, method, and computer program product for over-constraint/deadcode detection in a formal verification
    Patent number: 10706195
    Abstract: The present disclosure relates to a method for use in the formal verification of an electronic circuit. Embodiments may include receiving, using a processor, a portion of an electronic circuit design and analyzing a syntactic structure of a string associated with the electronic circuit design. Embodiments may also include generating a parse tree, based upon, at least in part, the analysis and traversing the parse tree to identify one or more conditional nodes. Embodiments may further include generating a new node for each of the one or more conditional nodes and displaying, at a graphical user interface, a check, at least one of the one or more conditional nodes or the new node prior to performing either register-transfer-level RTL synthesis or final synthesis.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: July 7, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Luis Humberto Rezende Barbosa, Raquel Lara dos Santos Pereira, Caio Alves Furtado, Breno Augusto Dias Vitorino, Mirlaine Aparecida Crepalde, Rodrigo da Silva Mantini Viana, Lucas Duarte Prates
  • System, method, and computer program product for property clustering associated with formal verification of an electronic circuit design
    Patent number: 10289798
    Abstract: The present disclosure relates to a method for debugging associated with formal verification of an electronic design. Embodiments may include performing, using a processor, an initial formal verification of an electronic design. Embodiments may further include identifying one or more counter-examples associated with one or more assertion properties of the electronic design or identifying one or more cover-traces associated with one or more cover properties of the electronic design. Embodiments may further include generating a trace core for each of the one or more counter-examples or cover-traces, wherein each trace core includes a minimal representation of the counter-example or cover-trace. Embodiments may further include identifying a similarity between a plurality of the trace cores and clustering the plurality of trace cores having the similarity.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: May 14, 2019
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ronalu Augusta Nunes Barcelos, Hudson Dyele Pinheiro de Oliveira, Mirlaine Aparecida Crepalde, Lucas Luz Reckziegel, Glauber Tadeu de Sousa Carmo, Augusto Amaral Mafra, Regina Mara Amaral Fonseca, Guilherme Henrique de Sousa Santos, Valdir Antoniazzi Júnior