Abstract: In a feedback-type buffer amplifier designed to be interposed between a reference voltage source and a capacitive load, the output of the amplifier is applied to each of two precisely matched or scaled source follower circuits. The voltages appearing at respective output nodes of the source follower circuits are designed to be identical to each other. But, significantly, the nodes are decoupled from each other. One output node is included in the feedback path of the buffer amplifier, whereas the other node constitutes the output terminal of the composite arrangement. Perturbations or phase shifts due to the load are thus effectively decoupled from the feedback path of the amplifier. A fast-settling stable overall configuration is thereby provided.

Abstract: In a conventional CMOS integrated circuit such as a switched capacitor filter, power supply noise signals are coupled from the substrate to high impedance nodes via various parasitic capacitances. To minimize these noise signals and thereby improve the power supply rejection ratio of the circuit, only N-channel transistors are coupled to the nodes. Additionally, the P-tubs of these transistors are connected to an on-chip regulated power supply. Moreover, for certain metallic runners and capacitors of the circuit that are connected to the specified nodes and parasitically coupled to the substrate, grounded P-tubs are formed directly under the runners and capacitors.

Abstract: In a PCM CODEC, a binary-weighted charge redistribution capacitor array is designed to be configured for either .mu.-law or A-law coding. Selection of one or the other coding configuration is achieved by controlling a single gate circuit. A unique cascaded switch arrangement ensures that when selected capacitors representative of a specified coding segment are connected to a reference voltage source, the next successive capacitor of the array is automatically connected to a variable source that provides a voltage representative of a step within the specified segment.

Abstract: Improved input offset voltage compensation of an amplifier (12) is achieved through the use of a servo loop which is added to electronic switch and capacitor offset compensation circuitry disposed in the input (14) and feedback (20) paths of the amplifier. A voltage approximately equal to the offset voltage is stored on a feedback capacitor (24) by operation of input reset (34), feedback shunt (22) and feedback reset (26) switches. An error correction voltage is then generated within the servo loop (40) to adjust for the residual offset produced by the operation of the input reset and feedback shunt switches as well as the finite gain of the amplifier.

Abstract: Offset voltage compensation is provided by a feedback capacitor (24) in a feedback loop (20). For periodically resetting the compensation, the signal input terminal (14) is grounded by an electronic MOSFET switch (34). Other such switches (22, 26) close the feedback loop (20) in front of the capacitor (24) and connect the output side of the capacitor (24) to ground for recharging. An input capacitor (30) for compensating the switching feed-through charge of the feedback loop switch (22) is connected between the input signal source (32) and the signal input terminal (14). The ratio of the inherent capacitances of the switches (22, 34) is equal to the capacitance ratio of their respective capacitors (24, 30). Also disclosed is a particularly advantageous method for operating the switches. For switching from the reset condition back to the transmit condition, first the feedback loop switch (22) is opened. Thereafter, the other switches (26, 31, 34) are operated.