Patents by Inventor Miron Drobnis

Miron Drobnis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8357971
    Abstract: A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: January 22, 2013
    Assignee: NXP B.V.
    Inventors: Steven Thomas Peake, Philip Rutter, Christopher Martin Rogers, Miron Drobnis, Andrew Butler
  • Publication number: 20100320532
    Abstract: A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.
    Type: Application
    Filed: October 22, 2008
    Publication date: December 23, 2010
    Applicant: NXP B.V.
    Inventors: Steven Thomas Peake, Philip Rutter, Christopher Martin Rogers, Miron Drobnis, Andrew Butler
  • Patent number: 6784488
    Abstract: A metal-oxide-semiconductor trench-gate semiconductor device in which a substantially intrinsic region (40) is provided below the gate trench (20), which extends from the base of the trench, substantially across the drain drift region (14) towards the drain contact region (14a), such that when the drain-source voltage falls during turn-on of the device its rate of decrease is higher. This reduces the switching losses of the device. The substantially intrinsic region (40) may, for example, be formed by implanting a region below the trench (20) with a damage implant.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Eddie Huang, Miron Drobnis, Martin J. Hill, Raymond J. E. Hueting
  • Patent number: 6781156
    Abstract: A localised reduced lifetime region (1,25,41) is provided in a semiconductor device formed substantially of silicon. A predetermined concentration of carbon is provided in the region, and then the body is heated to incorporate a lifetime controlling impurity substantially within the carbon region. It is believed that the association between the impurity ions (M+) and the carbon atoms (C) on silicon lattice sites produces C-M+ complexes with significant capture cross-sections. The carbon may be provided by addition during epitaxial growth of silicon material, during bulk growth of the silicon, or by implantation and/or diffusion.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: August 24, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Miron Drobnis, Martin J. Hill
  • Publication number: 20030127645
    Abstract: A localised reduced lifetime region (1,25,41) is provided in a semiconductor device formed substantially of silicon. A predetermined concentration of carbon is provided in the region, and then the body is heated to incorporate a lifetime controlling impurity substantially within the carbon region. It is believed that the association between the impurity ions (M+) and the carbon atoms (C) on silicon lattice sites produces C-M+ complexes with significant capture cross-sections. The carbon may be provided by addition during epitaxial growth of silicon material, during bulk growth of the silicon, or by implantation and/or diffusion.
    Type: Application
    Filed: December 10, 2002
    Publication date: July 10, 2003
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Miron Drobnis, Martin J. Hill
  • Publication number: 20030094650
    Abstract: A metal-oxide-semiconductor trench-gate semiconductor device in which a substantially intrinsic region (40) is provided below the gate trench (20), which extends from the base of the trench, substantially across the drain drift region (14) towards the drain contact region (14a), such that when the drain-source voltage falls during turn-on of the device its rate of decrease is higher. This reduces the switching losses of the device. The substantially intrinsic region (40) may, for example, be formed by implanting a region below the trench (20) with a damage implant.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 22, 2003
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS
    Inventors: Eddie Huang, Miron Drobnis, Martin J. Hill, Raymond J.E. Hueting