Abstract: A memory controlling device configured to connect to a first memory module including a resistance switching memory cell array which is partitioned into a plurality of partitions and a second memory module used for a cache is provided. A cache controller splits an address of a read request into at least a first cache index and a first tag, and determines whether the read request is a cache hit or a cache miss by referring to a lookup logic based on the first cache index and the first tag. The cache controller instructs the memory controller to read target data of the read request from the first memory module when the read request targets to the second partition in a case where the read request is the cache miss and a write to the first partition is in progress.

Abstract: A memory controlling device of a computing device including a CPU, a memory, and a flash-based storage device is provided. The memory controlling device includes an address manager and an interface. The address manager aggregates a memory space of the memory and a storage space of the storage device into an expanded memory space, and handles a memory request for the expanded memory space from the CPU by using the memory space of the memory as a cache for the storage space of the storage device. The interface is used to access the memory and the storage device.