Patents by Inventor Misa Awano

Misa Awano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120052646
    Abstract: A semiconductor device 1 according to one embodiment of the invention includes: a semiconductor substrate 10; a convex region 12 provided on the semiconductor substrate 10; a gate insulating film 100 provided on the convex region 12; a channel region 101 located in the convex region 12 under the gate insulating film 100; source/drain regions 115 provided on both sides of the convex region 12 and having extensions 115a on both sides of the channel region 101; and a halo layer 110 provided between the convex region 12 and the source/drain region 115 so as to contact with the convex region 12.
    Type: Application
    Filed: November 3, 2011
    Publication date: March 1, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Misa Awano
  • Patent number: 8076731
    Abstract: A semiconductor device 1 according to one embodiment of the invention includes: a semiconductor substrate 10; a convex region 12 provided on the semiconductor substrate 10; a gate insulating film 100 provided on the convex region 12; a channel region 101 located in the convex region 12 under the gate insulating film 100; source/drain regions 115 provided on both sides of the convex region 12 and having extensions 115a on both sides of the channel region 101; and a halo layer 110 provided between the convex region 12 and the source/drain region 115 so as to contact with the convex region 12.
    Type: Grant
    Filed: June 8, 2009
    Date of Patent: December 13, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Misa Awano
  • Publication number: 20090321851
    Abstract: A semiconductor device 1 according to one embodiment of the invention includes: a semiconductor substrate 10; a convex region 12 provided on the semiconductor substrate 10; a gate insulating film 100 provided on the convex region 12; a channel region 101 located in the convex region 12 under the gate insulating film 100; source/drain regions 115 provided on both sides of the convex region 12 and having extensions 115a on both sides of the channel region 101; and a halo layer 110 provided between the convex region 12 and the source/drain region 115 so as to contact with the convex region 12.
    Type: Application
    Filed: June 8, 2009
    Publication date: December 31, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Misa Awano