Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a program capable of reducing the number of pins for transmitting and receiving data. The signal processing apparatus is provided with a signal transmission unit configured to perform classification for a signal to be transmitted and received between processing units that process an obtained signal, perform time division multiplexing for the signal classified into a group, and transmit the signal. The classification is performed depending on at least one feature of an update period, an update timing, and a tolerable transmission delay of the signal. Further, the signal belonging to the group is subjected to time division multiplexing in such a manner that the transmission is completed within the update period, the transmission is completed within a range of the tolerable delay, and the transmission is performed with a minimum number of pins.

Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a program capable of reducing the number of pins for transmitting and receiving data. The signal processing apparatus is provided with a signal transmission unit configured to perform classification for a signal to be transmitted and received between processing units that process an obtained signal, perform time division multiplexing for the signal classified into a group, and transmit the signal. The classification is performed depending on at least one feature of an update period, an update timing, and a tolerable transmission delay of the signal. Further, the signal belonging to the group is subjected to time division multiplexing in such a manner that the transmission is completed within the update period, the transmission is completed within a range of the tolerable delay, and the transmission is performed with a minimum number of pins.

Abstract: The present technique relates to a demodulation device, a demodulation method and a program capable of realizing a demodulation process at a rate equivalent to a case where I and Q channel signals are not inverted, even when the I and Q channel signals are inverted. A frequency correction unit establishes synchronization of a frequency and clock based on a signal from a frequency synchronization unit. A channel inversion detection unit of a frame synchronization unit detects presence or absence of inversion of I and Q channel signals, and supplies, as a detection result, a channel inversion detection result to the channel inversion control unit. The channel inversion control unit switches the I and Q channel signals if the inversion has occurred, based on the channel inversion detection result. This technique can be applied to a demodulation device.

Abstract: The present technique relates to a demodulation device, a demodulation method and a program capable of realizing a demodulation process at a rate equivalent to a case where I and Q channel signals are not inverted, even when the I and Q channel signals are inverted. A frequency correction unit establishes synchronization of a frequency and clock based on a signal from a frequency synchronization unit. A channel inversion detection unit of a frame synchronization unit detects presence or absence of inversion of I and Q channel signals, and supplies, as a detection result, a channel inversion detection result to the channel inversion control unit. The channel inversion control unit switches the I and Q channel signals if the inversion has occurred, based on the channel inversion detection result. This technique can be applied to a demodulation device.

Abstract: The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adder 13 integrates the product of an information word D13 of six bits supplied from a cyclic shift circuit 12 and the information part of a check matrix H corresponding to the information for each row in a unit of six rows and supplies the integrated value as a sum D15 to a RAM 14. The RAM 14 stores the sum D15. Further, the RAM 14 successively reads out sums D16 of 2 bits stored already therein and supplies the read out sums D16 as sums D17 to an accumulator 16 through an interleaver 15. The accumulator 16 integrates the sums D17 and outputs a sum D18 obtained as a result of the integration as a parity bit p of a codeword c through a selector 17. The present invention can be applied to an apparatus of a broadcasting station which transmits a satellite broadcast.

Abstract: The present invention relates to a coding apparatus and a coding method by which the circuit scale can be reduced without changing the operation speed in coding of a linear code. An adder 13 integrates the product of an information word D13 of six bits supplied from a cyclic shift circuit 12 and the information part of a check matrix H corresponding to the information for each row in a unit of six rows and supplies the integrated value as a sum D15 to a RAM 14. The RAM 14 stores the sum D15. Further, the RAM 14 successively reads out sums D16 of 2 bits stored already therein and supplies the read out sums D16 as sums D17 to an accumulator 16 through an interleaver 15. The accumulator 16 integrates the sums D17 and outputs a sum D18 obtained as a result of the integration as a parity bit p of a codeword c through a selector 17. The present invention can be applied to an apparatus of a broadcasting station which transmits a satellite broadcast.