Patents by Inventor Misaichi Takeuchi

Misaichi Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9899565
    Abstract: A method of manufacturing a semiconductor substrate may include forming a first semiconductor layer on a growth substrate, forming a second semiconductor layer on the first semiconductor layer, forming a plurality of voids in the first semiconductor layer by removing portions of the first semiconductor layer that are exposed by a plurality of trenches in the second semiconductor layer, forming a third semiconductor layer on the second semiconductor layer and covering the plurality of trenches, and separating the second and third semiconductor layers from the growth substrate. on the first semiconductor layer. The third semiconductor layer are grown from the second semiconductor layer and extend above the second semiconductor layer.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Jo Tak, Sam Mook Kang, Mi Hyun Kim, Jun Youn Kim, Young Soo Park, Misaichi Takeuchi
  • Publication number: 20170069785
    Abstract: A method of manufacturing a semiconductor substrate may include forming a first semiconductor layer on a growth substrate, forming a second semiconductor layer on the first semiconductor layer, forming a plurality of voids in the first semiconductor layer by removing portions of the first semiconductor layer that are exposed by a plurality of trenches in the second semiconductor layer, forming a third semiconductor layer on the second semiconductor layer and covering the plurality of trenches, and separating the second and third semiconductor layers from the growth substrate. on the first semiconductor layer. The third semiconductor layer are grown from the second semiconductor layer and extend above the second semiconductor layer.
    Type: Application
    Filed: June 16, 2016
    Publication date: March 9, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young Jo TAK, Sam Mook KANG, Mi Hyun KIM, Jun Youn KIM, Young Soo PARK, Misaichi TAKEUCHI
  • Publication number: 20160118533
    Abstract: A method of manufacturing a nanostructure semiconductor light emitting device may include: stacking a mask layer on a conductive base layer and forming a through hole penetrating the mask layer; growing a nanocore through the through hole from the conductive base layer using precursor gas including indium-containing precursor gas in a mixed gas atmosphere of nitrogen and hydrogen; removing the mask layer; and sequentially growing an active layer and a first conductivity type semiconductor layer on a surface of the nanocore.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 28, 2016
    Inventors: MISAICHI TAKEUCHI, Sam Mook KANG, Shigeru INOUE, Ki Se KIM
  • Patent number: 8698168
    Abstract: A method of crystal growth is provided which can suppress development of dislocations and cracks and a warp in a substrate. The method of crystal growth of a group III nitride semiconductor has: a step of heating a silicon substrate; and a step of forming a depressed structure on the substrate surface by advance-feeding onto the heated silicon substrate a gas containing at least TMA (trimethylaluminum).
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: April 15, 2014
    Assignees: Sharp Kabushiki Kaisha, The Ritsumeikan Trust
    Inventors: Yoshihiro Ueta, Masataka Ohta, Yoshinobu Aoyagi, Misaichi Takeuchi
  • Publication number: 20120007039
    Abstract: A method of crystal growth is provided which can suppress development of dislocations and cracks and a warp in a substrate. The method of crystal growth of a group III nitride semiconductor has: a step of heating a silicon substrate; and a step of forming a depressed structure on the substrate surface by advance-feeding onto the heated silicon substrate a gas containing at least TMA (trimethylaluminum).
    Type: Application
    Filed: March 3, 2011
    Publication date: January 12, 2012
    Applicants: THE RITSUMEIKAN TRUST, SHARP KABUSHIKI KAISHA
    Inventors: Yoshihiro Ueta, Masataka Ohta, Yoshinobu Aoyagi, Misaichi Takeuchi
  • Patent number: 6530991
    Abstract: A method for the formation of a semiconductor layer by which a defect density of structural defects, particularly a dislocation density of threading dislocations in the resulting semiconductor layer can be remarkably reduced, so that hours of work can be shortened as well as a manufacturing cost can be reduced without requiring any complicated process comprises supplying a structural defect suppressing material for suppressing structural defects in the semiconductor layer onto a surface of the layer of a material from which the semiconductor layer is to be formed.
    Type: Grant
    Filed: December 13, 2000
    Date of Patent: March 11, 2003
    Assignees: Riken
    Inventors: Satoru Tanaka, Misaichi Takeuchi, Yoshinobu Aoyagi
  • Publication number: 20010012678
    Abstract: A method for the formation of a semiconductor layer by which a defect density of structural defects, particularly a dislocation density of threading dislocations in the resulting semiconductor layer can be remarkably reduced, so that hours of work can be shortened as well as a manufacturing cost can be reduced without requiring any complicated process comprises supplying a structural defect suppressing material for suppressing structural defects in the semiconductor layer onto a surface of the layer of a material from which the semiconductor layer is to be formed.
    Type: Application
    Filed: December 13, 2000
    Publication date: August 9, 2001
    Inventors: Satoru Tanaka, Misaichi Takeuchi, Yoshinobu Aoyagi