Patents by Inventor Misako Morota

Misako Morota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230413584
    Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
    Type: Application
    Filed: August 8, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Takahiko IIZUKA, Daisaburo TAKASHIMA, Ryu OGIWARA, Rieko FUNATSUKI, Yoshiki KAMATA, Misako MOROTA, Yoshiaki ASAO, Yukihiro NOMURA
  • Patent number: 11765916
    Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Takahiko Iizuka, Daisaburo Takashima, Ryu Ogiwara, Rieko Funatsuki, Yoshiki Kamata, Misako Morota, Yoshiaki Asao, Yukihiro Nomura
  • Publication number: 20230102229
    Abstract: According to one embodiment, a memory device includes a stacked structure including a plurality of conductive layers stacked to be apart from each other in a first direction, and a pillar structure including a resistance change portion extending in the first direction in the stacked structure, and a semiconductor portion which extends in the first direction in the stacked structure and which includes a first portion provided along the resistance change portion and a second portion extending from the first portion in at least one direction intersecting the first direction.
    Type: Application
    Filed: March 14, 2022
    Publication date: March 30, 2023
    Applicant: Kioxia Corporation
    Inventors: Yoshiki KAMATA, Yoshiaki ASAO, Yukihiro NOMURA, Misako MOROTA, Daisaburo TAKASHIMA, Takahiko IIZUKA, Shigeru KAWANAKA
  • Publication number: 20220093685
    Abstract: A semiconductor memory device, includes: a stack including a wiring layer and an insulation layer alternately stacked in a first direction; a semiconductor layer including a first region overlapping with the insulation layer in a second direction, and a second region overlapping with the wiring layer in the second direction; an insulation region between the wiring layer and the second region; and a memory region on the opposite side of the second region from the wiring layer. The wiring layer is farther from the first region in the second direction than the insulation layer is. The second region has a part between the insulation layers in the first direction and protruding further toward the wiring layer than the first region in the second direction. The memory region has a face opposite to the second region and closer to the wiring layer in the second direction than the first region is.
    Type: Application
    Filed: June 14, 2021
    Publication date: March 24, 2022
    Applicant: Kioxia Corporation
    Inventors: Yoshiki KAMATA, Misako MOROTA, Yukihiro NOMURA, Yoshiaki ASAO
  • Publication number: 20210399049
    Abstract: A memory device includes: a first interconnect; a second interconnect; a first string and a second string whose first ends are coupled to the first interconnect; a third string and a fourth string whose second ends are coupled to the second interconnect; a third interconnect; and driver. The third interconnect is coupled to second ends of the first and second strings and to first ends of the third and fourth strings. Each of the first, second, third, and fourth strings includes a first switch element and a memory cell coupled in series. The memory cell includes a second switch element and a resistance change element coupled in parallel. The third interconnect is coupled to the driver via the first interconnect or the second interconnect.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Takahiko IIZUKA, Daisaburo TAKASHIMA, Ryu OGIWARA, Rieko FUNATSUKI, Yoshiki KAMATA, Misako MOROTA, Yoshiaki ASAO, Yukihiro NOMURA
  • Patent number: 10559750
    Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive portion, an insulating film surrounding a side surface of the first conductive portion, an intermediate layer provided on the first conductive portion and the insulating film, a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state, and a second conductive portion provided at least on the resistance change portion.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: February 11, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Asao, Misako Morota, Yoshiki Kamata, Yukihiro Nomura, Iwao Kunishima
  • Publication number: 20190288193
    Abstract: According to one embodiment, a nonvolatile memory device includes a first conductive portion, an insulating film surrounding a side surface of the first conductive portion, an intermediate layer provided on the first conductive portion and the insulating film, a first film including a first portion provided on the intermediate layer and at least one second portion provided in the intermediate layer and outside an upper edge of the first conductive portion, the first film including, above the first conductive portion, a resistance change portion that has a first resistance state and a second resistance state having resistance higher than resistance in the first resistance state, and a second conductive portion provided at least on the resistance change portion.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 19, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki ASAO, Misako MOROTA, Yoshiki KAMATA, Yukihiro NOMURA, Iwao KUNISHIMA
  • Patent number: 10153429
    Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a third conductive layer intersecting the first conductive layer and the second conductive layer, and a resistance change layer including a first region which is provided between the first conductive layer and the third conductive layer and has a superlattice structure, a second region which is provided between the second conductive layer and the third conductive layer and has the superlattice structure, and a third region which is provided between the first region and the second region. The third region includes at least one element selected from the group consisting of O, F, C, P, B, N, H, Bi, Cd, Zn, Ga, Se, Al, S, Be, In, and Pb. Concentration of the at least one element in the third region is higher than that in the first region and the second region.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 11, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Yoshiki Kamata, Yoshiaki Asao, Iwao Kunishima, Misako Morota
  • Patent number: 9935122
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tsunehiro Ino, Daisuke Matsushita, Yasushi Nakasaki, Misako Morota, Akira Takashima, Kenichiro Toratani
  • Publication number: 20180006216
    Abstract: A memory device according to an embodiment includes a first conductive layer, a second conductive layer, a third conductive layer intersecting the first conductive layer and the second conductive layer, and a resistance change layer including a first region which is provided between the first conductive layer and the third conductive layer and has a superlattice structure, a second region which is provided between the second conductive layer and the third conductive layer and has the superlattice structure, and a third region which is provided between the first region and the second region. The third region includes at least one element selected from the group consisting of O, F, C, P, B, N, H, Bi, Cd, Zn, Ga, Se, Al, S, Be, In, and Pb. Concentration of the at least one element in the third region is higher than that in the first region and the second region.
    Type: Application
    Filed: June 28, 2017
    Publication date: January 4, 2018
    Inventors: Yoshiki KAMATA, Yoshiaki ASAO, Iwao KUNISHIMA, Misako MOROTA
  • Publication number: 20170077115
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a memory cell, the memory cell comprising: a semiconductor layer; a control gate electrode; a charge accumulation layer disposed between the semiconductor layer and the control gate electrode; a first insulating layer disposed between the semiconductor layer and the charge accumulation layer; and a second insulating layer disposed between the charge accumulation layer and the control gate electrode, the charge accumulation layer including an insulator that includes silicon and nitrogen, and the insulator further including: a first element or a second element, the second element being different from the first element; and a third element different from the first element and the second element.
    Type: Application
    Filed: March 16, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tsunehiro INO, Daisuke MATSUSHITA, Yasushi NAKASAKI, Misako MOROTA, Akira TAKASHIMA, Kenichiro TORATANI
  • Patent number: 9536898
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 3, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Misako Morota, Hideyuki Nishizawa, Masaya Terai, Shigeki Hattori, Koji Asakawa
  • Publication number: 20160240556
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
    Type: Application
    Filed: April 28, 2016
    Publication date: August 18, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Misako Morota, Hideyuki Nishizawa, Masaya Terai, Shigeki Hattori, Koji Asakawa
  • Patent number: 9356111
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: May 31, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Misako Morota, Hideyuki Nishizawa, Masaya Terai, Shigeki Hattori, Koji Asakawa
  • Patent number: 9349876
    Abstract: A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: May 24, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Izumi Hirano, Yuichiro Mitani, Masayasu Miyata, Yasushi Nakasaki, Koichi Kato, Daisuke Matsushita, Akira Takashima, Misako Morota
  • Publication number: 20150035045
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
    Type: Application
    Filed: October 20, 2014
    Publication date: February 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Misako MOROTA, Hideyuki NISHIZAWA, Masaya TERAI, Shigeki HATTORI, Koji ASAKAWA
  • Patent number: 8896052
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: November 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Misako Morota, Hideyuki Nishizawa, Masaya Terai, Shigeki Hattori, Koji Asakawa
  • Publication number: 20140167133
    Abstract: A nonvolatile semiconductor memory according to an embodiment includes: a semiconductor region; a first insulating film formed on the semiconductor region; a charge storage film formed on the first insulating film; a hydrogen diffusion preventing film formed on the charge storage film; a second insulating film formed on the hydrogen diffusion preventing film; a control gate electrode formed on the second insulating film; a hydrogen discharge film formed on the control gate electrode; and a sidewall formed on a side surface of a multilayer structure including the first insulating film, the charge storage film, the hydrogen diffusion preventing film, the second insulating film, and the control gate electrode, the sidewall containing a material for preventing hydrogen from diffusing.
    Type: Application
    Filed: December 17, 2013
    Publication date: June 19, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Izumi HIRANO, Yuichiro Mitani, Masayasu Miyata, Yasushi Nakasaki, Koichi Kato, Daisuke Matsushita, Akira Takashima, Misako Morota
  • Publication number: 20140061763
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; a tunnel insulating film that is formed on the semiconductor layer and includes a first organic molecular film including first organic molecules each having an alkyl molecular chain as the main chain; a charge storage layer formed on the tunnel insulating film, the charge storage layer being made of an inorganic material; a block insulating film formed on the charge storage layer; and a control gate electrode formed on the block insulating film.
    Type: Application
    Filed: December 26, 2012
    Publication date: March 6, 2014
    Inventors: Misako Morota, Hideyuki Nishizawa, Masaya Terai, Shigeki Hattori, Koji Asakawa
  • Publication number: 20130248962
    Abstract: A nonvolatile semiconductor memory device of an embodiment includes: a semiconductor layer; an organic molecular layer formed on the semiconductor layer, the organic molecular layer including a plurality of organic molecules, each of the organic molecules includes a tunnel insulating unit of alkyl chain having one end bonded to the semiconductor layer, a charge storing unit, and a bonding unit configured to bond the other end of the alkyl chain to the charge storing unit; a block insulating film formed on the organic molecular layer; and a gate electrode formed on the block insulating film.
    Type: Application
    Filed: September 4, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Misako Morota, Hideyuki Nishizawa, Shigeki Hattori, Masaya Terai, Koji Asakawa