Patents by Inventor Misao Hagiwara

Misao Hagiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141584
    Abstract: In order to provide artificial leather having both strength (in particular, tensile strength and tear strength), surface appearance, and a dense feeling in artificial leather including a fiber-entangled body containing a nonwoven fabric made of ultrafine fibers containing a large amount of inorganic particles (in particular, metal compounds) as a constituent element, and an elastic polymer, the artificial leather of the present invention is artificial leather including a fiber-entangled body containing a nonwoven fabric made of ultrafine fibers having an average single fiber diameter of 1.0 ?m or more and 10.0 ?m or less as a constituent element and an elastic polymer, and satisfies the following requirements: (1) the ultrafine fibers include a polyester-based resin containing a manganese-based compound; (2) an average particle diameter of the manganese-based compound is 0.01 ?m or more and 0.20 ?m or less; and (3) the ultrafine fibers contain a manganese element in an amount of 0.1 ppm or more and 50.
    Type: Application
    Filed: March 10, 2022
    Publication date: May 2, 2024
    Applicant: Toray Industries, Inc.
    Inventors: Haruka Oura, Tatsuya Hagiwara, Misao Omori, Yukihiro Matsuzaki
  • Patent number: 5194763
    Abstract: An output circuit comprises a plurality of output units respectively coupled between internal data signal lines and external data signal lines and assigned to respective bit positions, and a supervising circuit controlling the output units for supplying output data bits on the associated external data signal lines in a cascade manner; and each of the output units has a driving circuit operative to drive the associated external data signal line by providing a current path between the associated external data signal line and one of two sources of voltage level, and a control circuit responsive to an output data signal on the associated internal data signal line and allowing the driving circuit to drive the associated second data line, wherein the supervising circuit activates the controlling circuit of each output unit upon confirmation that the controlling circuit of another output unit assigned to the previous bit position has been activated.
    Type: Grant
    Filed: December 4, 1990
    Date of Patent: March 16, 1993
    Assignee: NEC Corporation
    Inventors: Kenichi Suzuki, Misao Hagiwara
  • Patent number: 4975651
    Abstract: A phase locked loop circuit for producing a control signal with a predetermined phase relationship to an input signal includes a first counter which counts a reference clock signal and is supplied from a control circuit with first and second signals. The first counter operates in a normal mode in which a count value is changed one by one when both, the first and second signals are not supplied, in a skip mode in which a first predetermined count value is skipped when the first signal is supplied, and in a repeat mode in which a second predetermined count value is repeated when the second signal is supplied. A second counter is provided, which perform a count operation in synchronism with the reference clock signal under the control of an output of the first counter to produce the control signal. The loop circuit further includes a phase comparator which produces phase difference data representative of a phase difference between the input signal and the control signal.
    Type: Grant
    Filed: June 12, 1989
    Date of Patent: December 4, 1990
    Assignee: NEC Corporation
    Inventor: Misao Hagiwara
  • Patent number: 4970405
    Abstract: A clock selection circuit for selecting and outputting one of several clock pulse signals supplied thereto includes a selector supplied with the clock pulse signals and with selection signals each corresponding to the clock pulse signals and selecting one of the clock pulse signals when a corresponding selection signal takes a selection level. A control circuit is supplied with selection data for producing the selection signals, one of which takes the selection level in response to the selection data. The control circuit responds to the change of the selection data for changing one of the selection signals from the selection level to the non-selection level without a substantial delay and another selection signal from the non-selection level to the selection level after a delay of at least one clock pulse of the clock pulse signal to be selected.
    Type: Grant
    Filed: December 12, 1988
    Date of Patent: November 13, 1990
    Assignee: NEC Corporation
    Inventor: Misao Hagiwara