Abstract: An imaging element according to an embodiment of the present disclosure includes a plurality of sensor pixels and a voltage control section. The sensor pixels each include a photoelectric conversion section, and a readout circuit that outputs a pixel signal based on charges outputted from the photoelectric conversion section. The voltage control section applies a control voltage based on the pixel signal to a plurality of the photoelectric conversion sections.

Abstract: A decrease in image quality is suppressed. A solid-state imaging apparatus according to an embodiment includes: a photoelectric conversion unit (PD) including a material having a smaller band gap energy than silicon; and a circuit board joined to the photoelectric conversion unit, the circuit board including: a pixel signal generation circuit that generates a pixel signal having a voltage value corresponding to a charge generated in the photoelectric conversion unit; and a thermometer circuit that detects a temperature of the circuit board.

Abstract: An imaging element according to an embodiment of the present disclosure includes a plurality of sensor pixels and a voltage control section. The sensor pixels each include a photoelectric conversion section, and a readout circuit that outputs a pixel signal based on charges outputted from the photoelectric conversion section. The voltage control section applies a control voltage based on the pixel signal to a plurality of the photoelectric conversion sections.

Abstract: An imaging device of the present disclosure includes: a plurality of pixels arranged side by side in a first direction and a second direction and each including a light receiving element; and a drive section configured to drive the plurality of pixels. Of the plurality of pixels, ones arranged side by side in the first direction have respective light receiving sensitivities equal to each other. Of the plurality of pixels, ones arranged side by side in the second direction include a first pixel and a second pixel each having a light receiving sensitivity, the light receiving sensitivity of the first pixel and the light receiving sensitivity of the second pixel being different from each other.

Abstract: Provided is an imaging device including: a pixel region including a first photoelectric converter; an outside-pixel region including a second photoelectric converter coupled to a predetermined electric potential; and a circuit substrate having one surface on which the first photoelectric converter and the second photoelectric converter are provided, and including a peripheral circuit electrically coupled to the first photoelectric converter.

Abstract: An imaging device of the present disclosure includes: a plurality of pixels arranged side by side in a first direction and a second direction and each including a light receiving element; and a drive section configured to drive the plurality of pixels. Of the plurality of pixels, ones arranged side by side in the first direction have respective light receiving sensitivities equal to each other. Of the plurality of pixels, ones arranged side by side in the second direction include a first pixel and a second pixel each having a light receiving sensitivity, the light receiving sensitivity of the first pixel and the light receiving sensitivity of the second pixel being different from each other.

Abstract: A clip mounting seat includes a mounting base having an outer edge, a mounting hole, and a mounting base-side insertion opening that is included at a part of a hole edge of the mounting hole and through which the clip is inserted to the mounting hole, a wall extending downward from the outer edge and including an insertion-side wall having a wall-side insertion hole communicated with the mounting base-side insertion opening, and a guide member included in the insertion-side wall and extending toward the mounting hole and being adjacent to the wall-side insertion hole and opposite the mounting base-side insertion opening with respect to an insertion direction of the clip. The guide member guides the clip and includes an end portion that is opposite the mounting base-side insertion opening and has a thickness greater than a distance between a leg portion and a support portion of the clip.

Abstract: A clip mounting seat includes a mounting base having an outer edge, a mounting hole in which the clip is mounted, and a mounting base-side insertion opening at a part of a hole edge of the mounting hole and through which the clip is inserted to the mounting hole, a wall extending downward from the outer edge and including an insertion-side wall having a wall-side insertion hole that is communicated with the mounting base-side insertion opening, and a guide member included in the insertion-side wall and extending along an extending direction of the insertion-side wall and being adjacent to the wall-side insertion hole and opposite the mounting base-side insertion opening with respect to an insertion direction of the clip, the guide member configured to guide the clip in the insertion direction and having a width that is greater than an opening width of the mounting base-side insertion opening.

Abstract: Provided is an imaging device including: a pixel region including a first photoelectric converter; an outside-pixel region including a second photoelectric converter coupled to a predetermined electric potential; and a circuit substrate having one surface on which the first photoelectric converter and the second photoelectric converter are provided, and including a peripheral circuit electrically coupled to the first photoelectric converter.

Abstract: A clip mounting seat includes a mounting base having an outer edge, a mounting hole, and a mounting base-side insertion opening that is included at a part of a hole edge of the mounting hole and through which the clip is inserted to the mounting hole, a wall extending downward from the outer edge and including an insertion-side wall having a wall-side insertion hole communicated with the mounting base-side insertion opening, and a guide member included in the insertion-side wall and extending toward the mounting hole and being adjacent to the wall-side insertion hole and opposite the mounting base-side insertion opening with respect to an insertion direction of the clip. The guide member guides the clip and includes an end portion that is opposite the mounting base-side insertion opening and has a thickness greater than a distance between a leg portion and a support portion of the clip.

Abstract: A clip mounting seat includes a mounting base having an outer edge, a mounting hole in which the clip is mounted, and a mounting base-side insertion opening at a part of a hole edge of the mounting hole and through which the clip is inserted to the mounting hole, a wall extending downward from the outer edge and including an insertion-side wall having a wall-side insertion hole that is communicated with the mounting base-side insertion opening, and a guide member included in the insertion-side wall and extending along an extending direction of the insertion-side wall and being adjacent to the wall-side insertion hole and opposite the mounting base-side insertion opening with respect to an insertion direction of the clip, the guide member configured to guide the clip in the insertion direction and having a width that is greater than an opening width of the mounting base-side insertion opening.

Abstract: To make it possible to appropriately set a capturing timing for a pixel value. For this, the present invention includes a pixel array unit 2 composed of pixels 21 arranged in a row direction and a column direction in a matrix manner and a latch unit 62 provided for each column constituting the pixel array unit 2 and configured to convert a pixel value of the pixel 21 into a digital pixel value to hold the pixel value. Also, the present invention includes a column scanning unit 4 for selecting the latch unit 62, a capturing unit 9 for sequentially capturing the pixel value held by the latch unit selected by the column scanning unit 4 in synchronism with a predetermined clock, and a delay unit 10 for delaying a clock for driving the capturing unit 9 in a plurality of stages. With the configuration described above, first dummy data is set in the latch unit 62-m at the near end, and second dummy data is set in the latch unit 62-0 at the far end.

Abstract: A clock adjustment circuit includes: first and third switching elements to be in a conductive state when in-phase and reverse-phase clock signals in a high level are applied to input terminals, respectively; second and fourth switching elements whose input terminals are connected to output terminals of the first and third switching elements, respectively, which become in the conductive state when the in-phase and reverse-phase clock signals in a low level are applied to output terminal, respectively; first and second capacitor elements whose one terminal is connected to an output terminal of the first and third switching element, respectively; and a shift detection unit detecting potential difference between the output terminals of the first and third switching elements and outputs the detection signal as a signal for adjusting a duty ratio of the clock signal.

Abstract: A clock adjustment circuit includes: first and third switching elements to be in a conductive state when in-phase and reverse-phase clock signals in a high level are applied to input terminals, respectively; second and fourth switching elements whose input terminals are connected to output terminals of the first and third switching elements, respectively, which become in the conductive state when the in-phase and reverse-phase clock signals in a low level are applied to output terminal, respectively; first and second capacitor elements whose one terminal is connected to an output terminal of the first and third switching element, respectively; and a shift detection unit detecting potential difference between the output terminals of the first and third switching elements and outputs the detection signal as a signal for adjusting a duty ratio of the clock signal.

Abstract: To make it possible to appropriately set a capturing timing for a pixel value. For this, the present invention includes a pixel array unit 2 composed of pixels 21 arranged in a row direction and a column direction in a matrix manner and a latch unit 62 provided for each column constituting the pixel array unit 2 and configured to convert a pixel value of the pixel 21 into a digital pixel value to hold the pixel value. Also, the present invention includes a column scanning unit 4 for selecting the latch unit 62, a capturing unit 9 for sequentially capturing the pixel value held by the latch unit selected by the column scanning unit 4 in synchronism with a predetermined clock, and a delay unit 10 for delaying a clock for driving the capturing unit 9 in a plurality of stages. With the configuration described above, first dummy data is set in the latch unit 62-m at the near end, and second dummy data is set in the latch unit 62-0 at the far end.

Abstract: A DLL circuit includes: an output dummy circuit having a prescribed propagation delay; a first delay element delaying a reference clock in accordance with a control signal and supplying the delayed signal to the output dummy circuit; a phase determination circuit comparing the phases of the reference clock and a feedback signal and supplying a control signal altering the delay amount of the first delay element; a second delay element receiving either the reference clock or the feedback signal, to serve as the trigger of the phase comparison operation, and delaying this signal by a delay amount; and a latch circuit latching the other signal not serving as the trigger of the phase comparison operation in synchronization with the rising edge of the output signal of the second delay element and supplying a signal turning on or off the input of the other signal to the phase determination circuit.

Abstract: In a duty ratio detecting apparatus, a duty ratio detecting circuit is constructed by first and second nodes, a load current supplying circuit for supplying first and second load currents to the first and second nodes, respectively, and a current switch connected to the first and second nodes. The current switch is operated in response to first and second complementary duty ratio signals. A duty ratio maintaining circuit is constructed by third and fourth nodes for receiving and maintaining voltages at the first and second nodes, respectively. A first switch is connected between the first and third nodes, and a second switch is connected between the second and fourth nodes. The load current supplying circuit is controlled by voltages at the third and fourth nodes.

Abstract: A DLL circuit includes: an output dummy circuit having a prescribed propagation delay; a first delay element delaying a reference clock in accordance with a control signal and supplying the delayed signal to the output dummy circuit; a phase determination circuit comparing the phases of the reference clock and a feedback signal and supplying a control signal altering the delay amount of the first delay element; a second delay element receiving either the reference clock or the feedback signal, to serve as the trigger of the phase comparison operation, and delaying this signal by a delay amount; and a latch circuit latching the other signal not serving as the trigger of the phase comparison operation in synchronization with the rising edge of the output signal of the second delay element and supplying a signal turning on or off the input of the other signal to the phase determination circuit.

Abstract: A flywheel, a cooling fan and a recoil starter are mounted on a crank shaft of an engine, thereby forming an engine unit. A power generating body is mounted on the end of the engine unit with the aid of an adapter intervening therebetween. The adapter and a rotor shaft are interconnected by means of a through bolt. A control system of the engine generator may be changed to an AVR type or an inverter type control system by removing the through bolt and replacing the power generating body with another. Accordingly, it is possible to provide an engine generator which allows the control system to be replaced with another type control system by easy replacing work.

Abstract: A DLL circuit includes: an output dummy circuit having a prescribed propagation delay; a first delay element delaying a reference clock in accordance with a control signal and supplying the delayed signal to the output dummy circuit; a phase determination circuit comparing the phases of the reference clock and a feedback signal and supplying a control signal altering the delay amount of the first delay element; a second delay element receiving either the reference clock or the feedback signal, to serve as the trigger of the phase comparison operation, and delaying this signal by a delay amount; and a latch circuit latching the other signal not serving as the trigger of the phase comparison operation in synchronization with the rising edge of the output signal of the second delay element and supplying a signal turning on or off the input of the other signal to the phase determination circuit.