Patents by Inventor Misato MIZOGUCHI

Misato MIZOGUCHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240227377
    Abstract: Provided is a method for manufacturing a laminate that is excellent in adhesion between the copper foil and the resin film while using a polyvinyl acetal resin having low reactivity with the copper foil. This method includes the steps of providing a copper foil having on at least one side a treated surface on which an amount of metal components is 30 atomic % or more and 40 atomic % or less, and attaching or forming a polyvinyl acetal resin film on the treated surface of the copper foil to form a laminate. The amount of metal components is a proportion of Cr, Ni, Cu, Zn, Mo, Co, W, and Fe in a total amount of N, O, Si, P, S, Cl, Cr, Ni, Cu, Zn, Mo, Co, W, and Fe when the treated surface is subjected to elemental analysis by X-ray photoelectron spectroscopy (XPS).
    Type: Application
    Filed: February 8, 2022
    Publication date: July 11, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Hiroto IIDA, Makoto HOSOKAWA, Misato MIZOGUCHI, Shinya HIRAOKA, Toshiyuki SHIMIZU
  • Patent number: 12004304
    Abstract: There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 ?m thick having a surface having an arithmetic mean waviness Wa of 0.10 ?m or more and 0.25 ?m or less as measured in accordance with JIS B0601-2001 and a kurtosis Sku of 2.0 or more and 3.5 or less as measured in accordance with ISO 25178; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.
    Type: Grant
    Filed: March 17, 2020
    Date of Patent: June 4, 2024
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori Shimizu, Hiroto Iida, Misato Mizoguchi, Akitoshi Takanashi, Makoto Hosokawa
  • Publication number: 20240131832
    Abstract: Provided is a method for manufacturing a laminate that is excellent in adhesion between the copper foil and the resin film while using a polyvinyl acetal resin having low reactivity with the copper foil. This method includes the steps of providing a copper foil having on at least one side a treated surface on which an amount of metal components is 30 atomic % or more and 40 atomic % or less, and attaching or forming a polyvinyl acetal resin film on the treated surface of the copper foil to form a laminate. The amount of metal components is a proportion of Cr, Ni, Cu, Zn, Mo, Co, W, and Fe in a total amount of N, O, Si, P, S, Cl, Cr, Ni, Cu, Zn, Mo, Co, W, and Fe when the treated surface is subjected to elemental analysis by X-ray photoelectron spectroscopy (XPS).
    Type: Application
    Filed: February 8, 2022
    Publication date: April 25, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Hiroto IIDA, Makoto HOSOKAWA, Misato MIZOGUCHI, Shinya HIRAOKA, Toshiyuki SHIMIZU
  • Publication number: 20240123707
    Abstract: Provided is a method for manufacturing a laminate that is excellent in adhesion between a copper foil and a resin film while using a polyvinyl acetal resin having low reactivity with the copper foil. This method includes the steps of providing a copper foil having a treated surface having a developed interfacial area ratio Sdr of 0.50% or more and 9.00% or less and a root mean square height Sq of 0.010 ?m or more and 0.200 ?m or less on at least one side, and attaching or forming a polyvinyl acetal resin film on the treated surface of the copper foil to form a laminate. The Sdr and Sq are values measured in accordance with ISO 25178 under conditions in which a cutoff wavelength of an S-filter is 0.55 ?m, and a cutoff wavelength of an L-filter is 10 ?m.
    Type: Application
    Filed: February 8, 2022
    Publication date: April 18, 2024
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Hiroto IIDA, Makoto HOSOKAWA, Misato MIZOGUCHI, Shinya HIRAOKA, Toshiyuki SHIMIZU
  • Publication number: 20220192029
    Abstract: There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 ?m thick having a surface having an arithmetic mean waviness Wa of 0.10 ?m or more and 0.25 ?m or less as measured in accordance with JIS B0601-2001 and a kurtosis Sku of 2.0 or more and 3.5 or less as measured in accordance with ISO 25178; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.
    Type: Application
    Filed: March 17, 2020
    Publication date: June 16, 2022
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori SHIMIZU, Hiroto IIDA, Misato MIZOGUCHI, Akitoshi TAKANASHI, Makoto HOSOKAWA
  • Publication number: 20220183158
    Abstract: There is provided a method for manufacturing a printed wiring board that effectively suppresses pattern failure and is also excellent in fine circuit forming properties. This method includes: providing an insulating substrate including a roughened surface; performing electroless plating on the roughened surface of the insulating substrate to form an electroless plating layer less than 1.0 ?m thick having a surface having an arithmetic mean waviness Wa of 0.10 ?m or more and 0.25 ?m or less and a valley portion void volume Vvv of 0.010 ?m3/?m2 or more and 0.028 ?m3/?m2 or less; laminating a photoresist on the surface of the electroless plating layer; performing exposure and development to form a resist pattern; applying electroplating to the electroless plating layer; stripping the resist pattern; and etching away an unnecessary portion of the electroless plating layer to form a wiring pattern.
    Type: Application
    Filed: March 17, 2020
    Publication date: June 9, 2022
    Applicant: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoshinori SHIMIZU, Hiroto IIDA, Misato MIZOGUCHI, Akitoshi TAKANASHI, Makoto HOSOKAWA