Abstract: There are provided a semiconductor and a method of fabricating the same. The semiconductor device may include a second semiconductor substrate directly bonded to a first semiconductor substrate. The first semiconductor substrate may include a first through via with an end portion protruding through a first top surface, the first top surface being a top surface of a first semiconductor substrate body, a liner extending to partially expose a side surface of the end portion of the first through via, and a first diffusion barrier layer. The liner may include a third top surface that is positioned at a lower height than a second top surface, the second top surface being a top surface of the end portion of the first through via and substantially equal to the first top surface. Alternatively, the liner may include a third surface positioned at a height that is lower than the second top surface and higher than the first top surface.

Abstract: In an embodiment, a semiconductor die includes a substrate, an interlayer insulating layer under a front-side surface the substrate, a horizontal metal interconnection in the interlayer insulating layer, a front-side pad under a lower surface of the interlayer insulating layer, a front-side bump structure under a lower surface of the front-side pad, a through-electrode vertically passing through the substrate, a back-side insulating layer over the back-side surface of the substrate, a first back-side metal plate layer over the back-side insulating layer, a back-side passivation layer over the back-side insulating layer and covering the first back-side metal plate layer, and a back-side bump structure over the through-electrode and the back-side passivation layer.

Abstract: A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

Abstract: A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

Abstract: A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

Abstract: A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.

Abstract: A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

Abstract: A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

Abstract: A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

Abstract: A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.

Abstract: There are provided a semiconductor and a method of fabricating the same. The semiconductor device may include a second semiconductor substrate directly bonded to a first semiconductor substrate. The first semiconductor substrate may include a first through via with an end portion protruding through a first top surface, the first top surface being a top surface of a first semiconductor substrate body, a liner extending to partially expose a side surface of the end portion of the first through via, and a first diffusion barrier layer. The liner may include a third top surface that is positioned at a lower height than a second top surface, the second top surface being a top surface of the end portion of the first through via and substantially equal to the first top surface. Alternatively, the liner may include a third surface positioned at a height that is lower than the second top surface and higher than the first top surface.

Abstract: A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

Abstract: A semiconductor chip may include: a body portion with a front surface and a rear surface; a pair of through electrodes penetrating the body portion; an insulating layer disposed over the rear surface of the body portion and the pair of through electrodes; and a rear connection electrode disposed over the insulating layer and connected simultaneously with the pair of through electrodes, wherein a distance between the pair of through electrodes is greater than twice a thickness of the insulating layer.

Abstract: The present invention relates to a method for determining the presence or absence of M. tuberculosis, M. bovis, and M. bovis BCG in a sample comprising a nucleic acid molecule. A method according to the present invention can detect the individual presence of M. tuberculosis, M. bovis, and M. bovis BCG, and the co-presence of two thereof.

Abstract: Provided is a shoulder brace having a forearm part, an upper-arm part, a torso part, an elbow-joint part, and a shoulder-joint part. The upper-arm part includes a rotary annulus to be coupled to an outside of the shoulder-joint part, the rotary annulus having line-shaped protrusions and grooves that are alternately formed along an inner circumference thereof. The shoulder-joint part includes a joint shaft, a push button provided on a first end thereof and coupled with the joint shaft, a locking ring coupled to a middle portion of the joint shaft and having line-shaped protrusions and grooves that are alternately formed along an outer circumference thereof, and a stopper formed on a second end thereof and providing space to allow the joint shaft to be movable when the push button is pushed, thus allowing a lock state to be released.