Abstract: An improved masking stack (63) comprises a pad oxide (58), polysilicon (60) and nitride (62). After forming a photoresist pattern (64) over the stack (63), an anisotropic etch is performed to remove the nitride (62) and a portion of the polysilicon (60) not covered by the pattern (64). Another etch is performed to remove the remaining polysilicon (60) to leave at least a portion of the pad oxide (58). A boron implant (66) is conducted to form implant areas (68 and 70) within the unmasked silicon active device layer (56). A portion of the implant areas (68 and 70) is masked with nitride (72), and the unmasked silicon layer (56) is then etched. The masking stack (63) and the nitride (72) is removed and unprotected silicon layer (56) and implant areas (68 and 70) are covered with an oxide forming the silicon dioxide mesa (78).

Abstract: The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.

Abstract: A new way of making sidewall channel stops for silicon on insulator devices (including silicon on oxide, silicon on nitride, and silicon on sapphire devices). While the moat regions 11, 13 (where the active devices will be formed) are covered by thick masking material 24, a high energy implantation step introduces additional doping into exposed silicon regions 14'. Before the mesa etch is performed to isolate the individual active device regions 32 a filament 28 is formed on the walls of the masking material 24 which covers the predetermined locations of the active device regions 32. The mesa etch is then performed using a chemistry which will be blocked not only by the original masking material 24 but also by the sidewall filaments 28. Thus, the doping level defined by implantation into regions 14' will extend into the sidewalls of the mesas 32 for a distance which is controlled not only by the lateral diffusion length of those dopants, but also by the thickness of the sidewall filament 28.