Patents by Inventor Miso SHIN

Miso SHIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Gap-fill layers, methods of forming the same, and semiconductor devices manufactured by the methods of forming the same
    Patent number: 11640922
    Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.
    Type: Grant
    Filed: January 19, 2022
    Date of Patent: May 2, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Miso Shin, Chungki Min, Gihwan Kim, Sanghyeok Kim, Hyo-Jung Kim, Geunwon Lim
  • GAP-FILL LAYERS, METHODS OF FORMING THE SAME, AND SEMICONDUCTOR DEVICES MANUFACTURED BY THE METHODS OF FORMING THE SAME
    Publication number: 20220139766
    Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.
    Type: Application
    Filed: January 19, 2022
    Publication date: May 5, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Miso SHIN, Chungki MIN, Gihwan KIM, Sanghyeok KIM, Hyo-Jung KIM, Geunwon LIM
  • Gap-fill layers, methods of forming the same, and semiconductor devices manufactured by the methods of forming the same
    Patent number: 11257708
    Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: February 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Miso Shin, Chungki Min, Gihwan Kim, Sanghyeok Kim, Hyo-Jung Kim, Geunwon Lim
  • Three-dimensional semiconductor memory device
    Patent number: 10916554
    Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: February 9, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Miso Shin, Myeongan Kwon, Chungki Min, Byoungho Kwon, Boun Yoon
  • THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20200185398
    Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Miso SHIN, Myeongan KWON, Chungki MIN, Byoungho KWON, Boun YOON
  • GAP-FILL LAYERS, METHODS OF FORMING THE SAME, AND SEMICONDUCTOR DEVICES MANUFACTURED BY THE METHODS OF FORMING THE SAME
    Publication number: 20200075398
    Abstract: A device including a gap-fill layer may include an upper layer that on a lower layer that defines a trench that extends from a top surface of the upper layer and towards the lower layer, and the gap filling layer may be a multi-layered structure filling the trench. The gap-filling layer may include a first dielectric layer that fills a first portion of the trench and has a top surface proximate to the top surface of the upper layer, a second dielectric layer that fills a second portion of the trench and has a top surface proximate to the top surface of the upper layer and more recessed toward the lower layer than the top surface of the first dielectric layer, and a third dielectric layer that fills a remaining portion of the trench and covers the top surface of the second dielectric layer.
    Type: Application
    Filed: April 8, 2019
    Publication date: March 5, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Miso SHIN, Chungki MIN, Gihwan KIM, Sanghyeok KIM, Hyo-Jung KIM, Geunwon LIM
  • Three-dimensional semiconductor memory device and method of fabricating the same
    Patent number: 10566338
    Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Miso Shin, Myeongan Kwon, Chungki Min, Byoungho Kwon, Boun Yoon
  • THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
    Publication number: 20190074282
    Abstract: Provided are a three-dimensional semiconductor memory device and a method of fabricating the same. The device may include a substrate including a peripheral circuit region and a cell array region, peripheral gate stacks provided on the peripheral circuit region of the substrate, and an electrode structure provided on the cell array region of the substrate. The electrode structure may include a lower electrode, a lower insulating layer covering the lower electrode, and upper electrodes and upper insulating layers, which are vertically and alternately stacked on the lower insulating layer. The lower insulating layer may be extended from the cell array region to the peripheral circuit region to cover the peripheral gate stacks, and a top surface of the lower insulating layer may be higher on the peripheral circuit region than on the cell array region.
    Type: Application
    Filed: March 15, 2018
    Publication date: March 7, 2019
    Inventors: Miso SHIN, Myeongan KWON, Chungki MIN, Byoungho KWON, Boun YOON