Abstract: A magnetic write head having a shield structure that provides both a leading shield and side shielding function. The magnetic shield is separated from the sides and leading edge of the write pole by a non-magnetic gap layer that has a non-uniform thickness. The non-magnetic gap layer is thicker near the leading edge and thinner at the trailing edge. This allows for increased side field gradient near the trailing edge of the write pole and decreased write field loss at the leading edge of the write pole.

Abstract: A magnetic write head having a shield structure that provides both a leading shield and side shielding function. The magnetic shield is separated from the sides and leading edge of the write pole by a non-magnetic gap layer that has a non-uniform thickness. The non-magnetic gap layer is thicker near the leading edge and thinner at the trailing edge. This allows for increased side field gradient near the trailing edge of the write pole and decreased write field loss at the leading edge of the write pole.

Abstract: Embodiments of the present invention help to suppress etching damage to a non-magnetic intermediate layer in manufacturing steps of a reproducing head. In one embodiment, a reproducing head has two junction insulating films between side ends of magnetoresistive sensor and hard bias films at both left and right of a track width direction of the magnetoresistive sensor. The reproducing head has first junction insulating films in addition to second junction insulating films.

Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

Abstract: A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

Abstract: A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.

Abstract: Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.

Abstract: An integrated semiconductor device has an improved reliability and is adapted to a higher degree of integration without reducing the accumulated electric charge of each information storage capacity element. The semiconductor device is provided with a DRAM having memory cells, each comprising an information storage capacity element C connected in series to a memory cell selection MISFET Qs formed on a main surface of a semiconductor substrate 1 and having a lower electrode 54, a capacity insulating film 58 and an upper electrode 59. The lower electrode 54 is made of ruthenium film oriented in a particular plane bearing, e.g., a (002) plane, and the capacity insulating film 58 is made of a polycrystalline tantalum film obtained by thermally treating an amorphous tantalum oxide film containing crystal of tantalum oxide in an as-deposited state for crystallization.

Abstract: A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.