Abstract: Methods and apparatus are provided for a Universal functionality Module (UFM). The apparatus comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for universally interfacing the PLD with any effectuator device. The UFM loads a startup personality bit stream from a boot memory, which allows it to read a pin configuration associated with a effectuator device. The UFM receives a function personality associated with the pin configuration, writes the function personality to programmable logic device, and initiates the function personality.

Abstract: A space telescope system includes, but is not limited to, a support platform configured to orbit astronomical object, a plurality of mirrors mounted to the support platform and spaced apart from one another, the plurality of mirrors being configured to reflect a plurality of focused beams, and a focal plane image combiner positioned to intersect the plurality of focused beams and configured to combine the plurality of focused beams to form a composite image.

Abstract: Systems and apparatus are provided for interfacing a digital controller with an analog input means. The system comprises a digital controller with the input of the digital controller coupled to the output of the analog-to-digital converter. The system further comprises a digital-to-analog converter coupled to an analog interface circuit. The analog interface circuit comprises a reconfigurable RC network switchably coupled to a first amplifier or to a second amplifier. The analog interface circuit further comprises a third amplifier having an input being coupled to an output of the second amplifier and the output of the third amplifier being coupled to the one or more input signal paths to the first amplifier.

Abstract: Systems and apparatus are provided for a reconfigurable, multi-purpose input/output (I/O) interface. The system comprises a comparator coupled to a means for signal generation. The system further comprises a switch fabric configured to reconfigure the I/O circuit in real time to perform a variety of signal processing, signal generation and built-in-test functions.

Abstract: Systems and apparatus are provided for interfacing a digital controller with an analog input means. The system comprises a digital controller with the input of the digital controller coupled to the output of the analog-to-digital converter. The system further comprises a digital-to-analog converter coupled to an analog interface circuit. The analog interface circuit comprises a reconfigurable RC network switchably coupled to a first amplifier or to a second amplifier. The analog interface circuit further comprises a third amplifier having an input being coupled to an output of the second amplifier and the output of the third amplifier being coupled to the one or more input signal paths to the first amplifier.

Abstract: Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

Abstract: Processor assemblies and modules are provided. One processor assembly includes first and second processors, and first and second input/output (I/O) interfaces coupled to the first and second processors. The first and/or second I/O interfaces are configured to compare outputs of the first and second processors, and render the first and second processors inactive if the outputs are different. One processor module includes first and second buses coupled to first and second processor assemblies. The first processor assembly includes first and second processors coupled to first and second I/O interfaces, wherein the first I/O interface is coupled to the first bus and the second I/O interface is coupled to the second bus. The second processor assembly includes third and fourth processors coupled to third and fourth I/O interfaces, wherein the third I/O interface is coupled to the first bus and the fourth I/O interface is coupled to the second bus.

Abstract: Systems and methods for validating predetermined events in reconfigurable control systems are provided. One method includes receiving, by a plurality of redundant processors operating in a first mode, a notice from two of three redundant sensors that the predetermined event occurred and reconfiguring the plurality of redundant processors to operate in a second mode in response to the notice. Another method includes receiving a first notice that one or more sensors detected that a first vehicle is coupled to a second vehicle at a primary control system and a secondary control system and reconfiguring the primary control system and the secondary control system to operate in another mode at substantially the same time in response to the notice.

Abstract: Reconfigurable virtual backplane systems and methods are provided. One virtual backplane system includes a bus, and first and second line cards coupled to the bus. Each line card includes a processor including a memory storing an array of configuration tables. Each configuration table stores a listing of processes to be transmitted to or received from the communication bus, wherein a first configuration table is selected from the first line card upon the occurrence of a first event and a second configuration table is selected from the second line card upon the occurrence of a second event. One method includes connecting first and second buses in first and second systems, respectively, to form a bus for a new system. The method further includes detecting the connection of the first and second buses, and reconfiguring the first and second systems to operate as the new system in response to detecting the connection.

Abstract: Processor assemblies and modules are provided. One processor assembly includes first and second processors, and first and second input/output (I/O) interfaces coupled to the first and second processors. The first and/or second I/O interfaces are configured to compare outputs of the first and second processors, and render the first and second processors inactive if the outputs are different. One processor module includes first and second buses coupled to first and second processor assemblies. The first processor assembly includes first and second processors coupled to first and second I/O interfaces, wherein the first I/O interface is coupled to the first bus and the second I/O interface is coupled to the second bus. The second processor assembly includes third and fourth processors coupled to third and fourth I/O interfaces, wherein the third I/O interface is coupled to the first bus and the fourth I/O interface is coupled to the second bus.

Abstract: Systems and methods for mapping a surface of a celestial body containing objects and terrain are provided. One system includes a Synthetic Aperture RADAR (SAR) module configured to capture a high-resolution image of the terrain of at least a portion of the surface and a map module configured to store map data representing the portion of the surface. The system also includes a fusion module configured to combine the high-resolution image and the map data to generate a high-resolution map of the portion of the surface. A method includes orbiting the celestial body, capturing, via the SAR module, a high-resolution image during each orbit, and fusing the captured high-resolution image with a low-resolution map of the surface to generate a high-resolution map of the surface. A computer-readable medium for storing instructions that cause a processor to perform the above method is also provided.

Abstract: A node comprises a host computer operable to execute application tasks and to transmit data; a local time-triggered Ethernet switch operable to enforce temporal constraints on time-triggered data; and a time-triggered Ethernet controller coupled to the local time-triggered Ethernet switch and operable to be coupled to a time-triggered Ethernet switch in each of a plurality of other control nodes.

Abstract: Devices systems and methods are provided for providing a deterministic remote interface unit (RIU) based on a finite state machine. The RIU emulator uses a sequence controller that is configured to receive a synchronization input and to execute a fixed list of unconditional commands in an invariable order of execution based solely upon the synchronization input. The RIU emulator also uses pre-defined or pre-certified data structures that are specific to one or more interface devices to successfully execute the at least one unconditional command of the plurality when encountered in the invariable order. As such, peripheral devices may be added, removed or updated without recertification by merely inserting pre-certified data structures into memory or deleting them.

Abstract: A robot for accomplishing a mission in a physical environment includes a body; and an operating system coupled to the body and configured to operate the body. The operating system is divided into a plurality of partitions, which includes a simulation partition configured to receive inputs and simulate the mission in a simulated environment corresponding to the physical environment based on the inputs to produce a simulated result, and a mission partition configured to receive the simulated result and determine actions to accomplish the mission based on the simulated result.

Abstract: Systems and methods for mapping a surface of a celestial body containing objects and terrain are provided. One system includes a Synthetic Aperture RADAR (SAR) module configured to capture a high-resolution image of the terrain of at least a portion of the surface and a map module configured to store map data representing the portion of the surface. The system also includes a fusion module configured to combine the high-resolution image and the map data to generate a high-resolution map of the portion of the surface. A method includes orbiting the celestial body, capturing, via the SAR module, a high-resolution image during each orbit, and fusing the captured high-resolution image with a low-resolution map of the surface to generate a high-resolution map of the surface. A computer-readable medium for storing instructions that cause a processor to perform the above method is also provided.