Abstract: In a data processor, the conditions associated with an operand are evaluated only in response to the execution of a special instruction. The results of this evaluation is provided as a result operand and stored in a general purpose destination register. The evaluated conditions are each provided in discrete form, that is, unencoded, rather than in encoded form.

Abstract: A pipelined data unit for use in a data processor, the data unit having special input operand check logic for involking a precise exception handling mechanism if either or both of the input operands fails the check, and output result format logic for involking an imprecise exception handling mechanism if the output result cannot be provided in a selected format. Special buffers are also provided to allow the control and status information unique to each instruction to flow through the pipeline together with that instruction. Sufficient information relating to each instruction being executed in the data unit is retained and made readily available to the handlers, so that each type of exception may be handled, should recovery be possible.

Abstract: A circuit for use in conjunction with a multiplier receives a portion of completed product bits and a portion of sum and carry bits which, when accumulated, provide a complete output product operand. The circuit is adaptable for use with input operands having single or double precision data formats. The accumulation time required depends upon which data format mode the circuit is operating in.