Abstract: In one embodiment, a core logic section of an integrated circuit is switched to be powered by a standby mode power voltage lower than a normal mode power voltage when the circuit is switched into a standby mode. The standby mode power voltage, however, is too low relative to normal ground to drive a transition logic section of the circuit. A special ground bus is provided in the transition logic section. The special ground bus is pulled down to a voltage below normal ground (i.e., a negative voltage) when the circuit is switched to the standby mode.

Abstract: A core logic portion of a clocked digital circuit is switched to be powered by a standby mode power voltage lower than a normal mode power voltage when the circuit is switched into a low power standby mode (LPSM). The standby mode power voltage is too low relative to normal ground to deterministically drive a transition logic portion of the circuit. However, a special ground bus (GNDx) is provided in the transition logic portion and that special ground bus (GNDx) is pulled down to a negative voltage below normal ground when the circuit is switched into the low power standby mode (LPSM).

Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

Abstract: Circuit models for the simulation of charge pumps facilitate design of integrated circuits containing charge pumps. Such models facilitate accurate simulation of actual charge pump behavior without the need to rigorously simulate the multiple capacitive stages of an actual charge pump and the dedicated oscillator clocking the charge pump. The various embodiments utilize a charge pump model having multiple pull-up stages. At lower output voltages, the pull-up stages each provide an output current. These output currents are added together as the output current of the charge pump. Each pull-up stage automatically shuts off when the output voltage approaches a dedicated voltage source for that pull-up stage. As the output voltage increases, less current is output due to the deactivation of pull-up stages.

Abstract: A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.

Abstract: A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.

Abstract: A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current flowing in the bit line. The output voltage of the current-to-voltage converter is compared to a reference voltage derived from the output of a reference current-to-voltage converter whose input is driven by a reference current on a reference bit line. Any cell that conducts more current than the reference current will be regarded as an erased cell. Conversely, any cell that conducts less current than the reference current will be regarded as a programmed cell.

Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

Abstract: Circuit models for the simulation of charge pumps facilitate design of integrated circuits containing charge pumps. Such models facilitate accurate simulation of actual charge pump behavior without the need to rigorously simulate the multiple capacitive stages of an actual charge pump and the dedicated oscillator clocking the charge pump. The various embodiments utilize a charge pump model having multiple pull-up stages. At lower output voltages, the pull-up stages each provide an output current. These output currents are added together as the output current of the charge pump. Each pull-up stage automatically shuts off when the output voltage approaches a dedicated voltage source for that pull-up stage. As the output voltage increases, less current is output due to the deactivation of pull-up stages.

Abstract: Circuit models for the simulation of charge pumps facilitate design of integrated circuits containing charge pumps. Such models facilitate accurate simulation of actual charge pump behavior without the need to rigorously simulate the multiple capacitive stages of an actual charge pump and the dedicated oscillator clocking the charge pump. The various embodiments utilize a charge pump model having multiple pull-up stages. At lower output voltages, the pull-up stages each provide an output current. These output currents are added together as the output current of the charge pump. Each pull-up stage automatically shuts off when the output voltage approaches a dedicated voltage source for that pull-up stage. As the output voltage increases, less current is output due to the deactivation of pull-up stages.

Abstract: A plurality of memory devices can be erase block tagged in parallel by issuing an erase pulse to memory devices that do not have memory blocks with erase block latches that indicate the block is erased. The status of the memory block is read after the erase pulse. If there are blocks remaining to be erased, erase block tag patterns are generated. Each memory block at a particular sector address has a unique erase block tag pattern to set the erase block latch for that particular memory block. The patterns are transmitted in parallel to the memory devices in a data burst.

Abstract: A master block lock control word is written to a mini array of non-volatile fuses. The control word is recalled and decoded. A successful recall of the control word generates an indication that the master block lock bit is permanently disabled from subsequent changes.

Abstract: A master block lock control word is written to a mini array of non-volatile fuses. The control word is recalled and decoded. A successful recall of the control word generates an indication that the master block lock bit is permanently disabled from subsequent changes.

Abstract: Circuit models for the simulation of charge pumps facilitate design of integrated circuits containing charge pumps. Such models facilitate accurate simulation of actual charge pump behavior without the need to rigorously simulate the multiple capacitive stages of an actual charge pump and the dedicated oscillator clocking the charge pump. The various embodiments utilize a charge pump model having multiple pull-up stages. At lower output voltages, the pull-up stages each provide an output current. These output currents are added together as the output current of the charge pump. Each pull-up stage automatically shuts off when the output voltage approaches a dedicated voltage source for that pull-up stage. As the output voltage increases, less current is output due to the deactivation of pull-up stages.