Abstract: An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.

Abstract: An ESD protection circuit (38) for a MOS device uses at least one electrically floating-base N+P-N+ transistor (43) connected between a metal bonding pad (40) and ground. The electrically floating base region (44) of each transistor is formed by a thin oxide region deposited over a substrate (50) of the MOS device. Because its N+ regions (42, 45) are made symmetrical about the floating base, each transistor conducts ESD pulses of both polarities equally. The beta of each transistor is made sufficiently large to withstand short-duration ESD current spikes. Current density is minimized by diffusing a deep N- well (54, 56) into each N+ region of each transistor to provide a larger effective conducting area. Low capacitance and higher breakdown voltage are achieved by eliminating the gate structure of prior art FET-based protection circuits.