Abstract: A system is disclosed for providing a platform for optimizing overlay location over programming content that is distributed over a channel by a content provider and displayed on a display at an establishment, the system comprising one or more servers that communicates with a client over a network, each server including one or more processors, memory and one or more programs stored in the memory, the one or more programs comprising instructions for: generating an overlay with information in response to a request from a user via the client that communicates with the one or more servers over the network; and positioning the overlay over programming content from the content provider that is distributed over the channel and displayed on the display at the establishment, wherein the overlay is positioned over programming content so that the overlay does not interfere with one or more tickers transmitted by the content provider over the programming content.

Abstract: A system is disclosed for providing a platform for optimizing overlay location over programming content that is distributed over a channel by a content provider and displayed on a display at an establishment, the system comprising one or more servers that communicates with a client over a network, each server including one or more processors, memory and one or more programs stored in the memory, the one or more programs comprising instructions for: generating an overlay with information in response to a request from a user via the client that communicates with the one or more servers over the network; and positioning the overlay over programming content from the content provider that is distributed over the channel and displayed on the display at the establishment, wherein the overlay is positioned over programming content so that the overlay does not interfere with one or more tickers transmitted by the content provider over the programming content.

Abstract: The state of cached data may be modified without performing a tag comparison. Each cache line includes at least one attribute bit and at least one state bit. A processor issues an instruction requesting modification of the state of all cache lines associated with an attribute specified by the instruction. Qualifying logic modifies the state of a cache line as a function of the attributes stored in the cache line and the attribute specified by the instruction.

Abstract: The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected.

Abstract: The system and method described provide for the detection and protection of memory accesses without the overhead typically incurred by memory management units. The processor includes a guarded memory unit, which monitors memory accesses to be performed by monitoring transmissions across the memory bus. The guarded memory unit includes a plurality of registers which identify memory addresses and modes which can cause a memory protection or detection violation to occur. If a memory protection violation occurs, a cancel signal is issued to cancel the memory operation prior to completion in order to protect the memory from unauthorized accesses. If a memory violation is detected, the memory operation is permitted to complete and a fault signal is issued to the processor to identify that a memory violation has been detected.

Abstract: A microprocessor bus arbitration communications scheme for enhancing efficiency and performance of a multi-master bus system, typically within a computer system, including a central processing unit ("CPU") being a primary bus master, a bus arbiter and at least one alternative bus master coupled together by a bus. The CPU includes an internal memory element, a bus queue and bus control logic which collectively operate to generate a plurality of microprocessor bus arbitration signals to the bus arbiter. These microprocessor bus arbitration signals include a first bus arbitration signal indicating whether the CPU requires access to the bus and a second bus arbitration signal indicating that the CPU requires immediate access to the bus.