Abstract: Embodiments of quantum ring oscillator-based coherence preservation circuits including a cascaded set of stages are described. Embodiments of such quantum ring oscillator-based coherence preservation circuits allow the internal (superpositioned) quantum state information of stored qubits to be preserved over long periods of time and present options for the measurement and potential correction of both deterministic and non-deterministic errors without disturbing the quantum information stored in the structure itself.

Abstract: Embodiments of feedback-based quantum circuits are described. Embodiments of such quantum circuits may be externally controlled using only basis or eigenstate (classically-observable) signals without triggering de-coherence. Additionally, embodiments of such quantum circuits allow the internal (superpositioned) quantum state information to be preserved over long periods of time and present options for quantum error-correction due to the basis-state controls. Moreover, a coupling of two such feedback-based quantum circuits allows for quantum-channel-based information exchange to a variety of ends.

Abstract: Methods, apparatuses, and computer program products for squaring an operand include identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit string. A square of the fixed-point value can be determined using the fixed point value, the substring size, and least significant bits of the fixed-point value equal to the substring size.

Abstract: Methods, apparatuses, and computer program products for squaring an operand include identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit string. A square of the fixed-point value can be determined using the fixed point value, the substring size, and least significant bits of the fix-point value equal to the substring size.

Abstract: Determining a table output of a table representing a hierarchical tree for an integer valued function includes determining an address from a table input. A subset of a memory is selected according to the address, where the memory represents the hierarchical tree and the subset represents a subtree of the hierarchical tree. Bit fields are selected from the subset, and bits are extracted from the bit fields. A table output is determined from the extracted bits.

Abstract: Determining a table output of a table representing a hierarchical tree for an integer valued function includes determining an address from a table input. A subset of a memory is selected according to the address, where the memory represents the hierarchical tree and the subset represents a subtree of the hierarchical tree. Bit fields are selected from the subset, and bits are extracted from the bit fields. A table output is determined from the extracted bits.

Abstract: A system and method for early evaluation in micropipeline processors to improve performance is provided. The present invention presents a design methodology where a micropipeline processor block (e.g., a binary full adder) is capable of computing a result based on the arrival of only a subset of inputs. In general, early evaluation allows micropipeline processor blocks to operate in parallel, where they might otherwise operate sequentially because of data arrival dependencies; thereby improving performance of the micropipeline processors.

Abstract: A system and method for early evaluation in micropipeline processors to improve performance is provided. The present invention presents a design methodology where a micropipeline processor block (e.g., a binary full adder) is capable of computing a result based on the arrival of only a subset of inputs. In general, early evaluation allows micropipeline processor blocks to operate in parallel, where they might otherwise operate sequentially because of data arrival dependencies; thereby improving performance of the micropipeline processors.