Abstract: Methods and systems for optimizing generation of natively executable code from non-native binary code are disclosed. One method includes receiving a source file including binary code configured for execution according to a non-native instruction set architecture. The method also includes translating one or more code blocks included in the executable binary code to source code, and applying an optimizing algorithm to instructions in the one or more code blocks. The optimizing algorithm is selected to reduce a number of memory address translations performed when translating the source code to native executable binary code, thereby resulting in one or more optimized code blocks. The method further includes compiling the source code to generate an output file comprising natively executable binary code including the one or more optimized code blocks.

Abstract: Methods and systems for optimizing generation of natively executable code from non-native binary code are disclosed. One method includes receiving a source file including binary code configured for execution according to a non-native instruction set architecture. The method also includes translating one or more code blocks included in the executable binary code to source code, and applying an optimizing algorithm to instructions in the one or more code blocks. The optimizing algorithm is selected to reduce a number of memory address translations performed when translating the source code to native executable binary code, thereby resulting in one or more optimized code blocks. The method further includes compiling the source code to generate an output file comprising natively executable binary code including the one or more optimized code blocks.

Abstract: A computing system and method of executing a software program and translation of instructions for an emulated computing environment. The computing system includes a programmable circuit capable of executing native instructions of a first instruction set architecture and incapable of executing non-native instructions of a second instruction set architecture. The emulator operates within an interface layer and translates non-native applications hosted within an emulated operating system for execution. The computing system includes translated memory banks defined at least in part by the emulated operating system and capable of native execution on the programmable circuit, where the emulated operating system is incapable of execution on the programmable circuit.

Abstract: Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system.

Abstract: Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.

Abstract: A system and method is disclosed for performing error recovery in a data processing system that supports multiple processing partitions. One or more processors and I/O modules, as well as a portion of the address space of a main memory, is allocated to each partition. In this type of configuration, requests generated by units of multiple partitions are processed by the same queue and state logic of the main memory. When a failure occurs within one processing partition, one or more units are identified as being directly affected by the fault. All requests and responses from, and to, the affected units, as well as any logical residue of these requests and responses are removed from the shared memory queue and state logic in a manner that allows the other partition to continue issuing requests and responses to the memory in a normal manner that does not involve recovery operations.

Abstract: An improved system and method for completing performance analysis for a target system is disclosed. According to the current invention, different types of configurations files are created, each to describe one or more respective aspects and/or portions of the target system. Each of these file types may include a combination of parameter values and equations that represent the respective portion of the system. After the configuration files are defined, scenarios are created. Each scenario includes a set of configuration files, with some or all of the files being of different file types. The files included within a scenario provide all parameter values and equations needed to calculate performance data for a particular revision of the target system. Next, a performance study is defined to include one or more of the scenarios. Finally, performance data is derived for each of the scenarios in the performance study.

Abstract: A memory control system and method is disclosed. In one embodiment, a first memory is coupled to one or more additional memories. The first memory receives requests for data that are completed by retrieving the data from the first memory and/or the one or more additional memories. The manner in which this data is retrieved is determined by the state of programmable control indicators. In one mode of operation, a reference is made to the first memory to retrieve the data. If it is later determined from tag information stored by the first memory that the one or more additional memories must be accessed to fulfill the request, the necessary additional memory references are initiated. In another mode of operation, references to the one or more additional memories are initiated irrespective of whether these references are required. The operating mode may be selected to optimize system efficiency.

Abstract: A system and method for managing memory data is provided. Data stored within a main memory may be requested by multiple requesters that may include one or more cache memories. When the data is provided by the main memory to a requester, it will be provided in a state that is based on the way the data was recently used by the requesters. For example, if a pattern of read-only usage has been established for the data, the data will be returned to a requester in a shared state. If data that was provided in a shared state must be updated such that the requester is required return to main memory to obtain read/write privileges, the main memory will thereafter provide the data in an exclusive state that allows write operations to be completed. This will continue until a pattern of read-only usage is again established.

Abstract: A system and method for testing and/or initializing a Directory Store in a directory-based coherent memory. In one illustrative embodiment, the directory-based coherent memory includes a Main Store for storing a number of data entries, a Directory Store for storing the directory state for at least some of the data entries in the Main Store, and a next state block for determining a next directory state for a requested data entry in response to a memory request. To provide access to the Directory Store, and in one illustrative embodiment, a selector is provided for selecting either the next directory state value provided by the next state block or another predetermined value. The other predetermined value may be, for example, a fixed data pattern, a variable data pattern, a specified value, or any other value suitable for initializing and/or testing the Directory Store. The output of the selector may be written to the Directory Store.

Abstract: The current invention provides a system and method for managing requests from one or more requesters to one or more resources. These requests, which may be any of multiple request types, are prioritized using one or more threshold values. Each threshold value is associated with one or more of the request types, and defines the maximum number of requests of the associated types that may be pending to the resources before the threshold is reached. When all associated thresholds have been reached for requests of one or more predetermined request types, an indication is provided to re-issue requests of those types at a later time. A priority scheme is used to allow re-issued requests to systematically gain access to the shared resource to prevent the starvation of any given requester.

Abstract: A system and method for managing memory data within a data processing system is disclosed. A main memory is provided to store data signals. When the main memory receives a request to read data signals, the main memory determines whether an updated copy of the requested data signals may be stored within some other storage device within the system. If so, the main memory issues a snoop request to this other storage device to cause any updated copy of the requested data to be returned to the main memory. In addition, the main memory reads the requested data signals from its data store. This data will be used to satisfy the read request if an updated copy of the data signals is not returned to the main memory in response to the snoop request. Otherwise, the updated copy is provided to fulfill the request.

Abstract: The current invention provides a system and method for managing data stored within a main storage device such as a main memory. In one embodiment, multiple requesters are coupled to the main storage device to store copies of ones of the data signals. A directory is coupled to the main storage device to store directory signals that describe the most recent copy of each the data signals. Another storage device is coupled to the directory to store a subset of the directory signals that describes a predetermined subset of the data signals. This subset of directory signals can be used to access any of the predetermined subset of the data signals in an accelerated manner.

Abstract: A dual-channel memory system and accompanying coherency mechanism is disclosed. The memory includes both a request and a response channel. The memory provides data to a requester such as an instruction processor via the response channel. If this data is provided for update purposes, other read-only copies of the data must be invalidated. This invalidation may occur after the data is provided for update purposes, and is accomplished by issuing one or more invalidation requests via one of the memory request or the response channel. Memory coherency is maintained by preventing a requester from storing any data back to memory until all invalidation activities that may be directly or indirectly associated with that data have been completed.

Abstract: Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning.

Abstract: A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel.

Abstract: An apparatus for and method of improving the efficiency of a level two cache memory. In response to a level one cache miss, a request is made to the level two cache. A signal sent with the request identifies when the requester does not anticipate a near term subsequent use for the requested data element. If a level two cache hit occurs, the requested data element is marked as least recently used in response to the signal. If a level two cache miss occurs, a request is made to level three storage. When the level three storage request is honored, the requested data element is immediately flushed from the level two cache memory in response to the signal.

Abstract: Poisoning of specific memory locations as a process when a part of a multiprocessor computer system becomes faulty leads to ability to isolate specific data owned by individual failing units even in a shared memory area. Also continuous processing by non-failing units is allowable. A support processor handles non-immediate problems and allows resetting of memory locations formerly owned by failed units.

Abstract: A directory-based cache coherency system is disclosed for use in a data processing system having multiple Instruction Processors (IP) and multiple Input/Output (I/O) units coupled through a shared main memory. The system includes one or more IP cache memories, each coupled to one or more IPs and to the shared main memory for caching units of data referred to as cache lines. The system further includes one or more I/O memories within ones of the I/O units, each I/O memory being coupled to the shared main memory for storing cache lines retrieved from the shared main memory. Coherency is maintained through the use of a central directory which stores status for each of the cache lines in the system. The status indicates the identity of the IP caches and the I/O memories having valid copies of a given cache line, and further identifies a set of access privileges, that is, the cache line “state”, associated with the cache line.

Abstract: Error correction and error detection related to DRAM chip failures, particularly adapted server memory subsystems. It uses ×4 bit DRAM devices organized in a code word of 128 data bit words and 16 check bits. These 16 check bits are generated in such a way as to provide a code capable of 4 bit adjacent error correction within a family (i.e., in a ×4 DRAM) and double bit non-adjacent error detection across the entire 128 bit word, with single bit correction across the word as well. Each device can be thought of as a separate family of bits, errors occurring in more than one family are not correctable, but may be detected if only one bit in each of two families is in error. Syndrome generation and regeneration are used together with a specific large code word. Decoding the syndrome and checking it against the regenerated syndrome yield data sufficient for providing the features described.