Abstract: A transcendental calculation unit includes a configuration table storing a set of constants and provide a selected one of the constants, a power series multiplier that iteratively develops a power series, a coefficient series multiplier and accumulator that develops an accumulated product of the power series and the constant, and a round and normalize stage that rounds the accumulated product and normalizes rounded product.

Abstract: A transcendental calculation unit includes a configuration table storing a set of constants and provide a selected one of the constants, a power series multiplier that iteratively develops a power series, a coefficient series multiplier and accumulator that develops an accumulated product of the power series and the constant, and a round and normalize stage that rounds the accumulated product and normalizes rounded product.

Abstract: A Transcendental Calculation Unit includes a Configuration Table storing a set of constants and provide a selected one of the constants, a Power Series Multiplier that iteratively develops a power series, a Coefficient Series Multiplier and Accumulator that develops an accumulated product of the power series and the constant, and a Round and Normalize Stage that rounds the accumulated product and normalizes rounded product.

Abstract: A system and method for binding instructions to a graphical processing unit (GPU) includes a GPU configured to receive bindlessly compiled instructions and interpret the bindlessly compiled instruction at runtime to identify a needed conversion The GPU generates a conversion information based on the bindlessly compiled instruction and needed conversion and converts the bindlessly compiled instruction according to the conversion information to generate a bound format instruction. The GPU may then execute the bound format instruction.

Abstract: A system and method for binding instructions to a graphical processing unit (GPU) includes a GPU configured to receive bindlessly compiled instructions and interpret the bindlessly compiled instruction at runtime to identify a needed conversion The GPU generates a conversion information based on the bindlessly compiled instruction and needed conversion and converts the bindlessly compiled instruction according to the conversion information to generate a bound format instruction. The GPU may then execute the bound format instruction.

Abstract: According to one general aspect, an apparatus may include a network of node circuits and a central arbiter circuit. The network of node circuits is within an integrated circuit, wherein the network includes a plurality of segments. The central arbiter circuit may be configured to schedule a routing of a message between a pair of node circuits in the network, wherein the routing includes a guaranteed latency between the pair of node circuits.

Abstract: A graphics processing unit may include a register file memory, a processing element (PE) and a load-store unit (LSU). The register file memory includes a plurality of registers. The PE is coupled to the register file memory and processes at least one thread of a vector of threads of a graphical application. Each thread in the vector of threads are processed in a non-stalling manner. The PE stores data in a first predetermined set of the plurality of registers in the register file memory that has been generated by processing the at least one thread and that is to be routed to a first stallable logic unit that is external to the PE. The LSU is coupled to the register file memory, and the LSU accesses the data in the first predetermined set of the plurality of registers and routes to the first stallable logic unit.

Abstract: A Transcendental Calculation Unit includes a Configuration Table storing a set of constants and provide a selected one of the constants, a Power Series Multiplier that iteratively develops a power series, a Coefficient Series Multiplier and Accumulator that develops an accumulated product of the power series and the constant, and a Round and Normalize Stage that rounds the accumulated product and normalizes rounded product.

Abstract: A graphics processing unit may include a register file memory, a processing element (PE) and a load-store unit (LSU). The register file memory includes a plurality of registers. The PE is coupled to the register file memory and processes at least one thread of a vector of threads of a graphical application. Each thread in the vector of threads are processed in a non-stalling manner. The PE stores data in a first predetermined set of the plurality of registers in the register file memory that has been generated by processing the at least one thread and that is to be routed to a first stallable logic unit that is external to the PE. The LSU is coupled to the register file memory, and the LSU accesses the data in the first predetermined set of the plurality of registers and routes to the first stallable logic unit.

Abstract: According to one general aspect, an apparatus may include a network of node circuits and a central arbiter circuit. The network of node circuits is within an integrated circuit, wherein the network includes a plurality of segments. The central arbiter circuit may be configured to schedule a routing of a message between a pair of node circuits in the network, wherein the routing includes a guaranteed latency between the pair of node circuits.

Abstract: A new system and method for high-speed testing of semiconductor devices is disclosed. The system utilizes bi-directional FET switches to hide the delay related to the distance signals have to travel between the test head electronics and the device under test. The effect is to increase the frequency with which a prior art tester can test a device. By placing the FET switches closer to the device under test, the device operates on the tester in the same electrical environment as it would in actual use. The device under test can be switched from receiving an input signal to driving an output signal in less time than the TL delay between the test head electronics and the device under test.

Abstract: The invention relates to a new system and method for high-speed testing of semiconductor devices. The system utilizes bi-directional switches to hide the delay related to the distance signals have to travel between the test head electronics and the device under test. The effect of the present invention is to increase the frequency with which a prior art tester can test a device.

Abstract: A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of the decode logic circuits decodes a first information and control signal set to enable a first memory bank to begin and complete a memory access operation. Each memory bank is comprised of a plurality of latch circuits (39,40, 42, 50) to store a predetermined information and control signal set necessary to perform the memory access operation. A second control signal and information set may, therefore, enable a second memory bank within the memory device (28) to perform a second memory access operation concurrently in time with the first memory access operation.