Abstract: The present disclosure describes a data center system including an instruction processing device for a chassis including one or more boards, a board including a set of cards, a card including a computing node or a processing device and a controller. The controller can receive an instruction from the instruction processing device through a first communication network between the controller and the instruction processing device. Based on the instruction, the processing device of the card can generate an operation result and provide the operation result to another device of the board through a second communication network different from the first communication network. The second communication network can have a ring topology or other topology. The instruction processing device can further operate a hierarchical manager to create a network manager to manage the operations of the board.

Abstract: The present disclosure describes a data center system including an instruction processing device for a chassis including one or more boards, a board including a set of cards, a card including a computing node or a processing device and a controller. The controller can receive an instruction from the instruction processing device through a first communication network between the controller and the instruction processing device. Based on the instruction, the processing device of the card can generate an operation result and provide the operation result to another device of the board through a second communication network different from the first communication network. The second communication network can have a ring topology or other topology. The instruction processing device can further operate a hierarchical manager to create a network manager to manage the operations of the board.

Abstract: A method and apparatus of stopping a functional block of an integrated circuit (IC) for debugging purposes is disclosed. In one embodiment, an IC includes a number of functional units accessible by an external debugger via a debug port (DP). During a debug operation, a power controller in the IC may power down a functional unit. When the functional unit is powered off, a first register may be programmed. Responsive to the programming of the first register, a first signal may be asserted and provided to the functional unit. When power is restored to the functional unit, operation of the functional unit may be halted prior to execution of instructions or other operations, responsive to the signal.

Abstract: A new pseudo network adapter is disclosed providing an interface for capturing packets from a local communications protocol stack for transmission on the virtual private network. The system further includes a Dynamic Host Configuration Protocol (DHCP) server emulator, and an Address Resolution Protocol (ARP) server emulator. The new system indicates to the local communications protocol stack that nodes on a remote private network are reachable through a gateway that is in turn reachable through the pseudo network adapter. The new pseudo network adapter includes a transmit path for processing data packets from the local communications protocol stack for transmission through the pseudo network adapter. The transmit path includes an encryption engine for encrypting the data packets and an encapsulation engine for encapsulating the encrypted data packets into tunnel data frames.