Patents by Inventor Mitchell PAGE

Mitchell PAGE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • THROUGH-GLASS VIA LINERS FOR INTEGRATED CIRCUIT DEVICE PACKAGES
    Publication number: 20250112163
    Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Pratyush Mishra, Pratyasha Mohapatra, Srinivas Pietambaram, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Yosef Kornbluth, Kuang Liu, Astitva Tripathi, Yuqin Li, Rengarajan Shanmugam, Xing Sun, Brian Balch, Darko Grujicic, Jieying Kong, Nicholas Haehn, Jacob Vehonsky, Mitchell Page, Vincent Obiozo Eze, Daniel Wandera, Sameer Paital, Gang Duan
  • THROUGH GLASS VIA (TGV) WITH MODULATED PROFILE FOR CORE STRESS REDUCTION
    Publication number: 20250113434
    Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. In an embodiment a corner at a junction between the sidewall and the first surface is rounded. In an embodiment, a via is provided in the opening, where the via is electrically conductive.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Bai NIE, Mitchell PAGE, Junxin WANG, Srinivas Venkata Ramanuja PIETAMBARAM, Haifa HARIRI, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Hongxia FENG, Haobo CHEN, Bohan SHAN, Hiroki TANAKA, Leonel R. ARANA, Yonggang Yong LI
  • STRESS MITIGATION ARCHITECTURES FOR GLASS CORE SUBSTRATES
    Publication number: 20250112140
    Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Rahul BHURE, Mitchell PAGE, Joseph PEOPLES, Jieying KONG, Nicholas S. HAEHN, Astitva TRIPATHI, Bainye Francoise ANGOUA, Yosef KORNBLUTH, Daniel ROSALES-YEOMANS, Joshua STACEY, Aaditya Anand CANDADAI, Yonggang Yong LI, Tchefor NDUKUM, Scott COATNEY, Gang DUAN, Jesse JONES, Srinivas Venkata Ramanuja PIETAMBARAM, Dilan SENEVIRATNE, Matthew ANDERSON
  • GLASS CORE PROTECTION USING PERIPHERAL BUFFER LAYERS
    Publication number: 20250112136
    Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
  • MICROELECTRONIC ASSEMBLIES WITH EDGE STRESS REDUCTION IN GLASS CORES
    Publication number: 20250112175
    Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Jesse C. Jones, Yosef Kornbluth, Mitchell Page, Soham Agarwal, Fanyi Zhu, Shuren Qu, Hanyu Song, Srinivas V. Pietambaram, Yonggang Li, Bai Nie, Nicholas Haehn, Astitva Tripathi, Mohamed R. Saber, Sheng Li, Pratyush Mishra, Benjamin T. Duong, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Haobo Chen, Robin Shea McRee, Mohammad Mamunur Rahman
  • NANOTWIN LINER FOR THROUGH GLASS VIAS
    Publication number: 20250106982
    Abstract: Embodiments disclosed herein include glass cores with through glass vias (TGVs). In an embodiment, an apparatus comprises a solid glass layer with an opening through a thickness of the layer, and a via in the opening. In an embodiment, the via comprises a first portion along sidewalls of the opening, where the first portion has a first microstructure, and a second portion in the opening, where the first portion surrounds the second portion, and where the second portion has a second microstructure that is different than the first microstructure.
    Type: Application
    Filed: September 25, 2023
    Publication date: March 27, 2025
    Inventors: Sashi S. KANDANUR, Mitchell PAGE, Nicholas S. HAEHN, Srinivas Venkata Ramanuja PIETAMBARAM, Steve S. CHO
  • Implant for repairing spinal annular defect, method of fabricating the implant, and method of repairing the defect using the implant
    Patent number: 12171670
    Abstract: A biocompatible implant, as well as method of fabricating the implant and repairing an annular defect in annulus fibrosus (AF) of an intervertebral disc (IVD) disposed in a functional spinal unit (FSU), includes an insert that provides faces that can interface with the defect to repair or treat the AF. The implant can deliver biological and mechanical factors to enhance healing in an annular defect and prevent recurrence of herniation symptoms. The implant can be fabricated using a hybrid of first fibrous scaffold structure including at least a first layer and a second layer of first fibers fabricated via three-dimensional fiber deposition (3FD) and second fibrous scaffold structure including a third layer and a fourth layer of second fibers formed via melt electrowriting (MEW). Suitable attachment methods, including bio-adhesives can be used to bond the implant to the IVD and/or FSU.
    Type: Grant
    Filed: October 5, 2021
    Date of Patent: December 24, 2024
    Assignee: COLORADO STATE UNIVERSITY RESEARCH FOUNDATION
    Inventors: Christian M. Puttlitz, Mitchell Page
  • IMPLANT FOR REPAIRING SPINAL ANNULAR DEFECT, METHOD OF FABRICATING THE IMPLANT, AND METHOD OF REPAIRING THE DEFECT USING THE IMPLANT
    Publication number: 20230372114
    Abstract: A biocompatible implant, as well as method of fabricating the implant and repairing an annular defect in annulus fibrosus (AF) of an intervertebral disc (IVD) disposed in a functional spinal unit (FSU), includes an insert that provides faces that can interface with the defect to repair or treat the AF. The implant can deliver biological and mechanical factors to enhance healing in an annular defect and prevent recurrence of herniation symptoms. The implant can be fabricated using a hybrid of first fibrous scaffold structure including at least a first layer and a second layer of first fibers fabricated via three-dimensional fiber deposition (3FD) and second fibrous scaffold structure including a third layer and a fourth layer of second fibers formed via melt electrowriting (MEW). Suitable attachment methods, including bio-adhesives can be used to bond the implant to the IVD and/or FSU.
    Type: Application
    Filed: October 5, 2021
    Publication date: November 23, 2023
    Inventors: Christian M. PUTTLITZ, Mitchell PAGE