Patents by Inventor Mitchell PAGE
Mitchell PAGE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260198346Abstract: Disclosed herein are microelectronic assemblies and related devices and methods for alleviating stresses in through-glass vias by providing double liner materials. In some embodiments, a microelectronic assembly may include a glass layer having a first surface and an opposing second surface; a via extending through the glass layer between the first and second surfaces, the via including a conductive material; a first liner, on a sidewall of the glass layer in the via, including a first inorganic material having a first Young's modulus; and a second liner, between the first liner and the conductive material of the via, including a second inorganic material having a second Young's modulus that is less than the first Young's modulus. In some embodiments, the first Young's modulus is between 25 Gigapascal (GPa) and 50 GPa, and the second Young's modulus is between 1 GPa and less than 25 GPa.Type: ApplicationFiled: January 6, 2025Publication date: July 9, 2026Applicant: Intel CorporationInventors: Joshua Stacey, Mahdi Mohammadighaleni, Mitchell Page, Thomas S. Heaton, Dilan Seneviratne
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Publication number: 20260191063Abstract: Semiconductor package substrates comprising solid amorphous glass layers are provided. The solid amorphous glass layers can have through-glass vias (TGVs) that include a layer of material that partially coats the walls of the vias. The partial coating can be on end regions of the through vias. Assemblies comprising these semiconductor package substrates and methods of manufacturing these semiconductor package substrates are provided.Type: ApplicationFiled: December 27, 2024Publication date: July 2, 2026Inventors: Joshua STACEY, Mahdi MOHAMMADIGHALENI, Mitchell PAGE, Jacob SCHICHTEL, Wei LI, Bai NIE, Thomas HEATON, Dilan SENEVIRATNE
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Publication number: 20260165174Abstract: Semiconductor package substrates comprising solid amorphous glass layers are provided. The solid amorphous glass layers can have through-glass vias (TGVs) that include a layer of material that has a coefficient of thermal expansion (CTE) that is similar to the CTE of the solid amorphous glass layer. Assemblies comprising these semiconductor package substrates and methods of manufacturing these semiconductor package substrates are provided.Type: ApplicationFiled: December 9, 2024Publication date: June 11, 2026Inventor: Mitchell PAGE
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Publication number: 20250183182Abstract: Various techniques for alleviating (e.g., mitigating or reducing) stresses between glass core materials and electrically conductive materials deposited in through-glass vias (TGVs) and related devices and methods are disclosed. In one aspect, a microelectronic assembly includes a glass core having a first face and a second face opposite the first face, and a TGV extending through the glass core between the first face and the second face, wherein the TGV includes a conductive material and a buffer layer between the conductive material and the glass core, wherein a CTE of the buffer layer is smaller than a CTE of the conductive material.Type: ApplicationFiled: November 30, 2023Publication date: June 5, 2025Inventors: Bohan Shan, Mahdi Mohammadighaleni, Joshua Stacey, Ehsan Zamani, Aaditya Candadai, Jacob Vehonsky, Daniel Wandera, Mitchell Page, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Jeremy Ecton, Brandon C. Marin, Onur Ozkan, Vinith Bejugam, Dhruba Pattadar, Amm Hasib, Nicholas Haehn, Makoyi Watson, Sanjay Tharmarajah, Jason M. Gamba, Yuqin Li, Astitva Tripathi, Mohammad Mamunur Rahman, Haifa Hariri, Shayan Kaviani, Logan Myers, Darko Grujicic, Elham Tavakoli, Whitney Bryks, Dilan Seneviratne, Bainye Angoua, Peumie Abeyratne Kuragama, Hongxia Feng, Kyle Jordan Arrington, Bai Nie, Jose Waimin, Ryan Carrazzone, Haobo Chen, Dingying Xu, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Bin Mu, Thomas S. Heaton, Rahul N. Manepalli
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Publication number: 20250112140Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a core with a first width, and the core comprises a glass layer. In an embodiment, a via is provided through a thickness of the core, where the via is electrically conductive. In an embodiment, a first layer is provided over the core, where the first layer comprises a second width that is smaller than the first width. In an embodiment, a second layer is provided under the core, where the second layer comprises a third width that is smaller than the first width.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Rahul BHURE, Mitchell PAGE, Joseph PEOPLES, Jieying KONG, Nicholas S. HAEHN, Astitva TRIPATHI, Bainye Francoise ANGOUA, Yosef KORNBLUTH, Daniel ROSALES-YEOMANS, Joshua STACEY, Aaditya Anand CANDADAI, Yonggang Yong LI, Tchefor NDUKUM, Scott COATNEY, Gang DUAN, Jesse JONES, Srinivas Venkata Ramanuja PIETAMBARAM, Dilan SENEVIRATNE, Matthew ANDERSON
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Publication number: 20250113434Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. In an embodiment a corner at a junction between the sidewall and the first surface is rounded. In an embodiment, a via is provided in the opening, where the via is electrically conductive.Type: ApplicationFiled: September 28, 2023Publication date: April 3, 2025Inventors: Bai NIE, Mitchell PAGE, Junxin WANG, Srinivas Venkata Ramanuja PIETAMBARAM, Haifa HARIRI, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Hongxia FENG, Haobo CHEN, Bohan SHAN, Hiroki TANAKA, Leonel R. ARANA, Yonggang Yong LI
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Publication number: 20250112175Abstract: Various techniques for edge stress reduction in glass cores and related devices and methods are disclosed. In one example, a microelectronic assembly includes a glass core having a bottom surface, a top surface opposite the bottom surface, and one or more sidewalls extending between the bottom surface and the top surface, and further includes a panel of an organic material, wherein the glass core is embedded within the panel. In another example, a microelectronic assembly includes a glass core as in the first example, where an angle between a portion of an individual sidewall and one of the bottom surface or the top surface is greater than 90 degrees. In yet another example, a microelectronic assembly includes a glass core as in the first example, and further includes a pattern of a material on one of the one or more sidewalls.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Brandon C. Marin, Jesse C. Jones, Yosef Kornbluth, Mitchell Page, Soham Agarwal, Fanyi Zhu, Shuren Qu, Hanyu Song, Srinivas V. Pietambaram, Yonggang Li, Bai Nie, Nicholas Haehn, Astitva Tripathi, Mohamed R. Saber, Sheng Li, Pratyush Mishra, Benjamin T. Duong, Kari Hernandez, Praveen Sreeramagiri, Yi Li, Ibrahim El Khatib, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Haobo Chen, Robin Shea McRee, Mohammad Mamunur Rahman
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Publication number: 20250112136Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Bohan SHAN, Jesse JONES, Zhixin XIE, Bai NIE, Shaojiang CHEN, Joshua STACEY, Mitchell PAGE, Brandon C. MARIN, Jeremy D. ECTON, Nicholas S. HAEHN, Astitva TRIPATHI, Yuqin LI, Edvin CETEGEN, Jason M. GAMBA, Jacob VEHONSKY, Jianyong MO, Makoyi WATSON, Shripad GOKHALE, Mine KAYA, Kartik SRINIVASAN, Haobo CHEN, Ziyin LIN, Kyle ARRINGTON, Jose WAIMIN, Ryan CARRAZZONE, Hongxia FENG, Srinivas Venkata Ramanuja PIETAMBARAM, Gang DUAN, Dingying David XU, Hiroki TANAKA, Ashay DANI, Praveen SREERAMAGIRI, Yi LI, Ibrahim EL KHATIB, Aaron GARELICK, Robin MCREE, Hassan AJAMI, Yekan WANG, Andrew JIMENEZ, Jung Kyu HAN, Hanyu SONG, Yonggang Yong LI, Mahdi MOHAMMADIGHALENI, Whitney BRYKS, Shuqi LAI, Jieying KONG, Thomas HEATON, Dilan SENEVIRATNE, Yiqun BAI, Bin MU, Mohit GUPTA, Xiaoying GUO
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Publication number: 20250112163Abstract: An IC die package includes a substrate comprising glass and a plurality of holes extending through the glass. A via metallization is present within the holes. A liner is between the via metallization and the glass. The liner can comprise a beta-titanium alloy layer, polymer hydrogel layer and an MXene seed layer, an organic material layer and a metal layer, or an organic material layer between first and second metal layers. A polymer layer may be formed by electrodeposition of charged nanoparticles.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Intel CorporationInventors: Pratyush Mishra, Pratyasha Mohapatra, Srinivas Pietambaram, Whitney Bryks, Mahdi Mohammadighaleni, Joshua Stacey, Travis Palmer, Yosef Kornbluth, Kuang Liu, Astitva Tripathi, Yuqin Li, Rengarajan Shanmugam, Xing Sun, Brian Balch, Darko Grujicic, Jieying Kong, Nicholas Haehn, Jacob Vehonsky, Mitchell Page, Vincent Obiozo Eze, Daniel Wandera, Sameer Paital, Gang Duan
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Publication number: 20250106982Abstract: Embodiments disclosed herein include glass cores with through glass vias (TGVs). In an embodiment, an apparatus comprises a solid glass layer with an opening through a thickness of the layer, and a via in the opening. In an embodiment, the via comprises a first portion along sidewalls of the opening, where the first portion has a first microstructure, and a second portion in the opening, where the first portion surrounds the second portion, and where the second portion has a second microstructure that is different than the first microstructure.Type: ApplicationFiled: September 25, 2023Publication date: March 27, 2025Inventors: Sashi S. KANDANUR, Mitchell PAGE, Nicholas S. HAEHN, Srinivas Venkata Ramanuja PIETAMBARAM, Steve S. CHO
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Patent number: 12171670Abstract: A biocompatible implant, as well as method of fabricating the implant and repairing an annular defect in annulus fibrosus (AF) of an intervertebral disc (IVD) disposed in a functional spinal unit (FSU), includes an insert that provides faces that can interface with the defect to repair or treat the AF. The implant can deliver biological and mechanical factors to enhance healing in an annular defect and prevent recurrence of herniation symptoms. The implant can be fabricated using a hybrid of first fibrous scaffold structure including at least a first layer and a second layer of first fibers fabricated via three-dimensional fiber deposition (3FD) and second fibrous scaffold structure including a third layer and a fourth layer of second fibers formed via melt electrowriting (MEW). Suitable attachment methods, including bio-adhesives can be used to bond the implant to the IVD and/or FSU.Type: GrantFiled: October 5, 2021Date of Patent: December 24, 2024Assignee: COLORADO STATE UNIVERSITY RESEARCH FOUNDATIONInventors: Christian M. Puttlitz, Mitchell Page
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Publication number: 20230372114Abstract: A biocompatible implant, as well as method of fabricating the implant and repairing an annular defect in annulus fibrosus (AF) of an intervertebral disc (IVD) disposed in a functional spinal unit (FSU), includes an insert that provides faces that can interface with the defect to repair or treat the AF. The implant can deliver biological and mechanical factors to enhance healing in an annular defect and prevent recurrence of herniation symptoms. The implant can be fabricated using a hybrid of first fibrous scaffold structure including at least a first layer and a second layer of first fibers fabricated via three-dimensional fiber deposition (3FD) and second fibrous scaffold structure including a third layer and a fourth layer of second fibers formed via melt electrowriting (MEW). Suitable attachment methods, including bio-adhesives can be used to bond the implant to the IVD and/or FSU.Type: ApplicationFiled: October 5, 2021Publication date: November 23, 2023Inventors: Christian M. PUTTLITZ, Mitchell PAGE
