Patents by Inventor Mitchell R. DeHond
Mitchell R. DeHond has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12112114Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.Type: GrantFiled: August 11, 2021Date of Patent: October 8, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Wolpert, Leon Sigal, Michael Stewart Gray, Mitchell R. DeHond
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Patent number: 11941340Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.Type: GrantFiled: August 16, 2021Date of Patent: March 26, 2024Assignee: International Business Machines CorporationInventors: Michael Alexander Bowen, Gerald L Strevig, III, Amanda Christine Venton, Robert Mahlon Averill, III, Adam P. Matheny, David Wolpert, Mitchell R. DeHond
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Patent number: 11822867Abstract: Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.Type: GrantFiled: August 13, 2021Date of Patent: November 21, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Wolpert, Leon Sigal, Michael Stewart Gray, Mitchell R. DeHond
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Publication number: 20230051392Abstract: Aspects of the invention include methods, systems, and computer program products for integrated circuit development using cross-hierarchy antenna condition verification. A method includes obtaining a design of a hierarchical macro distributed between multiple files for an integrated circuit and analyzing, by a design verification tool, a route between at least one child macro and at least one pin of the hierarchical macro as defined in the files. The method further includes determining, by the design verification tool, a plurality of connection characteristics of the at least one child macro and the at least one pin forming the route and calculating, by the design verification tool, an antenna condition for the route based on the connection characteristics. The design of the hierarchical macro is adjusted to remove a violation of an antenna rule based on determining that the antenna condition of the route violates the antenna rule.Type: ApplicationFiled: August 16, 2021Publication date: February 16, 2023Inventors: Michael Alexander Bowen, Gerald L Strevig, III, Amanda Christine Venton, Robert Mahlon Averill, III, Adam P. Matheny, David Wolpert, Mitchell R. DeHond
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Publication number: 20230050539Abstract: Aspects of the invention include a computer-implemented method of chip design. The computer-implemented method of chip design include establishing an architecture with alternating rows of differently colored chip-level shapes. Cells are constrained to be rectangular with restricted widths. Constraint-observing parent and child cells are generated and respectively include boundaries with alternating rows of differently colored cell-level shapes for disposition in the architecture. The parent cell is positioned in the architecture such that the cell-level shapes thereof exhibit row and color alignment with the chip-level shapes. Child cells exhibiting uni-axial or multi-axial reflectivity are instantiated in the parent cell. A color solution is instantiated for each child cell in the parent cell such that cell-level shapes of the child cells exhibit row and color alignment with the cell-level shapes of the parent cell.Type: ApplicationFiled: August 13, 2021Publication date: February 16, 2023Inventors: David Wolpert, Leon Sigal, Michael Stewart Gray, Mitchell R. DeHond
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Publication number: 20230050432Abstract: Aspects of the invention include systems and methods configured to provide hierarchical circuit designs that makes use of a color decomposition of library cells having boundary-aware color selection. A non-limiting example computer-implemented method includes placing a plurality of shapes within a hierarchical level of a chip design. The plurality of shapes can include a top boundary shape, a bottom boundary shape, one or more center boundary shapes, and one or more internal shapes. A hierarchical hand-off region is constructed by pinning the top boundary shape to a first mask, pinning the bottom boundary shape to a second mask, and pinning the one or more center boundary shapes to a same mask. The same mask is selected from one of the first mask and the second mask.Type: ApplicationFiled: August 11, 2021Publication date: February 16, 2023Inventors: David Wolpert, Leon Sigal, Michael Stewart Gray, Mitchell R. DeHond
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Publication number: 20170161425Abstract: Methodologies for compact modeling of circuit layouts to accurately account for effects of layout-induced changes in semiconductor devices induced by various intentional and unintentional mechanisms present in semiconductor processes are disclosed. The layout-sensitive compact model accounts for the impact of large layout variation on circuits by implementing techniques for obtaining the correct layout-dependent response approximations and by incorporating layout extraction techniques to obtain correct geometric parameters that drive the LDE response. In particular, these techniques include utilizing shape sections for analyzing in detail various specific region shapes of the semiconductor device. The shape sections are defined by locating vertices of each region shape and rendering reference lines at each vertex.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Inventors: Mitchell R. DeHond, Ulrich A. Finkler, Harold E. Reindel, Steven E. Washburn, Richard Q. Williams
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Patent number: 7584077Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: GrantFiled: June 18, 2004Date of Patent: September 1, 2009Assignee: International Business Machines CorporationInventors: Betty L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
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Patent number: 6823496Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: GrantFiled: April 23, 2002Date of Patent: November 23, 2004Assignee: International Business Machines CorporationInventors: Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
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Publication number: 20040221250Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: ApplicationFiled: June 18, 2004Publication date: November 4, 2004Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Betty L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox, Jr.
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Publication number: 20030200513Abstract: A system, method and media for locating and defining process sensitive sites isolated to specific geometries or shape configurations within chip design data. Once a systemic process sensitive site is identified, a 3D design checking deck is coded and executed through a design checker on physical design data. Target match shapes are produced and embedded back into the design data. Pictures, maps and coordinates of process sensitive sites are produced and sent to a website library for reference.Type: ApplicationFiled: April 23, 2002Publication date: October 23, 2003Applicant: International Business Machines CorporationInventors: Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Daniel N. Maynard, Brian D. Pfeifer, David C. Reynolds, Reginald B. Wilcox
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Patent number: 4627152Abstract: A method for automatically laying out a circuit starting from a logic gate diagram, especially for a CMOS technology. The logic is divided into blocks having a maximum number of serially connected transistors. Then the transistors are ordered to maximize the number of contiguously connected transistors. The ordered transistors then have their remaining connections determined according to the type of logic gate they represent.Type: GrantFiled: May 24, 1985Date of Patent: December 9, 1986Assignee: International Business Machines CorporationInventors: Mitchell R. DeHond, Paul J. Ledak