Patents by Inventor Mitchell Reid
Mitchell Reid has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11431359Abstract: A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.Type: GrantFiled: November 30, 2020Date of Patent: August 30, 2022Assignee: Silicon Laboratories Inc.Inventors: Michael A. Wu, Wentao Li, Mitchell Reid, John M. Khoury, Yan Zhou
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Publication number: 20220173756Abstract: A method for operating a radio frequency communications system includes, while operating a first radio frequency communications device in a calibration mode, for each setting of a plurality of settings of a programmable gain amplifier in a receiver of the first radio frequency communications device configured in a zero-intermediate frequency mode of operation, generating an estimate of a DC offset in each of a plurality of digital samples received from an analog circuit path including the programmable gain amplifier, and storing in a corresponding storage element, a compensation value based on the estimate.Type: ApplicationFiled: November 30, 2020Publication date: June 2, 2022Inventors: Michael A. Wu, Wentao Li, Mitchell Reid, John M. Khoury, Yan Zhou
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Patent number: 9036091Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.Type: GrantFiled: January 6, 2011Date of Patent: May 19, 2015Assignee: Silicon Laboratories Inc.Inventors: Alan F. Hendrickson, Alessandro Piovaccari, Ramin Khoini-Poorfard, Mitchell Reid, Frederick Alan Rush, Jean-Marc Guyot, David Le Goff, Michael Robert May, Henry William Singor, Qi Cai, Peter Jozef Vancorenland, Chunyu Xin, Pascal Blouin
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Publication number: 20120176550Abstract: An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.Type: ApplicationFiled: January 6, 2011Publication date: July 12, 2012Inventors: Alan F. Hendrickson, Alessandro Piovaccari, Ramin Khoini-Poorfard, Mitchell Reid, Frederick Alan Rush, Jean-Marc Guyot, David Le Goff, Michael Robert May, Henry William Singor, Qi Cai, Peter Jozef Vancorenland, Chunyu Xin, Pascal Blouin
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Patent number: 7889812Abstract: A receiver (1000) includes a direct digital frequency synthesizer (DDFS) (700) and first (1040) and second (1042) mixers. The DDFS (700) has a first output for providing a first local oscillator signal, and a second output for providing a second local oscillator signal offset from a quadrature relationship with the first local oscillator signal by a phase offset. The first mixer (1040) has a first input for receiving a radio frequency (RF) signal, a second input for receiving the first local oscillator signal, and an output for providing an in-phase signal at another frequency. The second mixer (1042) has a first input for receiving the RF signal, a second input for receiving the second local oscillator signal, and an output for providing a quadrature signal at the other frequency. The DDFS (700) may be implemented using first (702) and second (704) memories storing portions of a sinusoidal waveform and extra memories (706, 708) supporting the phase offset.Type: GrantFiled: May 26, 2006Date of Patent: February 15, 2011Assignee: Silicon Laboratories, Inc.Inventors: David S. Trager, Mitchell Reid
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Patent number: 7773968Abstract: A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal. The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310). The interface (134D) is coupled to the DDFS (132A) and is configured to align the bits provided by the DDFS (132A) with a first clock signal.Type: GrantFiled: November 30, 2006Date of Patent: August 10, 2010Assignee: Silicon Laboratories, Inc.Inventors: Adrian Maxim, Charles D. Thompson, Mitchell Reid
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Patent number: 7643600Abstract: A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output. The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input.Type: GrantFiled: November 30, 2006Date of Patent: January 5, 2010Assignee: Silicon Laboratories, Inc.Inventors: Adrian Maxim, Charles D. Thompson, Mitchell Reid
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Publication number: 20080130800Abstract: A receiver (300) includes a first mixing digital-to-analog converter (DAC) (336, 332), a second mixing DAC (338, 334), a direct digital frequency synthesizer (DDFS) (302), a phase correction circuit (340), a selectable load (306) and a magnitude correction circuit (350). The first mixing DAC (336, 332) includes a first input for receiving an input signal, a second input for receiving a digital first local oscillator (LO) signal and an output. The second mixing DAC (338, 334) includes a first input for receiving the input signal, a second input for receiving a digital second local oscillator (LO) signal and an output The DDFS (302) is configured to provide the first and second LO signals, which are quadrature signals. The phase correction circuit (340) is configured to provide a phase correction signal to a control input of the DDFS (302). The first selectable load (306) includes an input coupled to the output of the first mixing DAC (336, 332) and a control input.Type: ApplicationFiled: November 30, 2006Publication date: June 5, 2008Applicant: SILICON LABORATORIES, INC.Inventors: Adrian Maxim, Charles D. Thompson, Mitchell Reid
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Publication number: 20080132195Abstract: A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310).Type: ApplicationFiled: November 30, 2006Publication date: June 5, 2008Applicant: SILICON LABORATORIES, INC.Inventors: Adrian Maxim, Charles D. Thompson, Mitchell Reid
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Publication number: 20080123777Abstract: A receiver (1000) includes a direct digital frequency synthesizer (DDFS) (700) and first (1040) and second (1042) mixers. The DDFS (700) has a first output for providing a first local oscillator signal, and a second output for providing a second local oscillator signal offset from a quadrature relationship with the first local oscillator signal by a phase offset. The first mixer (1040) has a first input for receiving a radio frequency (RF) signal, a second input for receiving the first local oscillator signal, and an output for providing an in-phase signal at another frequency. The second mixer (1042) has a first input for receiving the RF signal, a second input for receiving the second local oscillator signal, and an output for providing a quadrature signal at the other frequency. The DDFS (700) may be implemented using first (702) and second (704) memories storing portions of a sinusoidal waveform and extra memories (706, 708) supporting the phase offset.Type: ApplicationFiled: May 26, 2006Publication date: May 29, 2008Applicant: SILICON LABORATORIES, INC.Inventors: David Trager, Mitchell Reid
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Patent number: 7089475Abstract: A communication isolation system is provided that may employ error correction techniques for the data communicated across an isolation barrier used for connecting electronic circuitry to a communication line. In one embodiment, each data bit to be transmitted to or from the phone line may be transmitted three times across an isolation barrier so that it is possible to withstand a single electronic fast transient event. In another embodiment, the isolation barrier may be a capacitive isolation barrier. In another embodiment, the three transmissions of the data bit may be received across the isolation barrier and delay elements utilized to provide the data bits to a logic circuit in a synchronized fashion so that the three data bits may be compared to determine the error corrected data.Type: GrantFiled: March 26, 2003Date of Patent: August 8, 2006Assignee: Silicon Laboratories Inc.Inventors: Andrew W. Krone, Mitchell Reid
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Patent number: 7020187Abstract: An improved modem architecture and associated method that integrates modem and line-isolation circuitry so as to achieve modem functionality and system-side isolation functionality on a single integrated circuit while also providing a modem interface that allows synchronous modem transmission protocols to be implemented through an asynchronous serial interface is disclosed. For example, one such type of synchronous modem transmission protocol is the HDLC (high-level data link control) protocol. According to the techniques disclosed herein, data and control information of an HDLC protocol may be presented at transmit and receive pins of a modem/system side DAA through an UART even though the UART may be an asynchronous serial receiver transmitter. Thus, both transmit and receive data transfers of a serial modem protocol may be implemented through an asynchronous serial interface.Type: GrantFiled: January 10, 2000Date of Patent: March 28, 2006Assignee: Silicon Laboratories Inc.Inventors: Mitchell Reid, Timothy J. Dupuis
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Patent number: 6826225Abstract: An improved modem architecture and associated method are disclosed that integrate modem functionality and line-side isolation functionality while also providing a modem interface that allows raw data, such as raw pulse-code-modulated (PCM) data, or modem data to be selectively communicated through a serial interface.Type: GrantFiled: January 10, 2000Date of Patent: November 30, 2004Assignee: Silicon Laboratories, Inc.Inventors: Timothy J. Dupuis, Andrew W. Krone, Mitchell Reid
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Patent number: 6735246Abstract: An improved modem architecture and associated method are disclosed that integrate modem functionality and line-side isolation functionality while also providing flow control of internal data between an isolation interface, digital-signal-processor (DSP) circuitry, and an analog input. The integrated modem and line-isolation circuit may also have an analog output for which data flow control is also provided.Type: GrantFiled: January 10, 2000Date of Patent: May 11, 2004Assignee: Silicon Laboratories Inc.Inventors: Timothy J. Dupuis, Andrew W. Krone, Mitchell Reid
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Patent number: 6714590Abstract: An improved modem architecture and associated method are disclosed that integrate modem and line-isolation circuitry so as to achieve modem functionality and system-side isolation functionality on a single integrated circuit.Type: GrantFiled: January 10, 2000Date of Patent: March 30, 2004Assignee: Silicon Laboratories, Inc.Inventors: Timothy J. Dupuis, Andrew W. Krone, Mitchell Reid
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Patent number: 6662238Abstract: An improved modem architecture and associated method are disclosed that integrate modem functionality and line-side isolation functionality while also providing a modem interface that allows command and data mode control.Type: GrantFiled: January 10, 2000Date of Patent: December 9, 2003Assignee: Silicon Laboratories Inc.Inventors: Timothy J. Dupuis, Mitchell Reid
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Patent number: 6304597Abstract: An improved modem architecture and associated method are disclosed that integrate modem functionality and line-side isolation functionality while allowing control of modem processing so that it may be bypassed if raw data, such as raw pulse-code-modulated (PCM) data, is desired to be transmitted or received.Type: GrantFiled: January 10, 2000Date of Patent: October 16, 2001Assignee: Silicon Laboratories, Inc.Inventors: Timothy J. Dupuis, Andrew W. Krone, Mitchell Reid