Patents by Inventor Mitesh Agrawal

Mitesh Agrawal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230174103
    Abstract: The method can include: receiving a set of inputs; determining a set of policies based on the set of inputs; determining a set of scores associated with the set of environmental policies; and evaluating the set of policies. Additionally or alternatively, the method can include operating the ego agent according to a selected policy and/or any other processes. The method functions to facilitate scoring of policies based on ‘feasibility’ for agents in an environment. Additionally or alternatively, the method can function to facilitate autonomous operation of a vehicle (e.g., based on policy-feasibility of agents in the environment). Additionally or alternatively, the method can function to facilitate intention estimation for agents in an environment.
    Type: Application
    Filed: December 1, 2022
    Publication date: June 8, 2023
    Inventors: Sajan Patel, Ahmed Elshaarany, Mitesh Agrawal, Alan Heirich, Edwin B. Olson
  • Patent number: 10658062
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10598526
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: March 24, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Patent number: 10586606
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: January 2, 2019
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Publication number: 20200005883
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Application
    Filed: September 11, 2019
    Publication date: January 2, 2020
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10365132
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: July 30, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Publication number: 20190156907
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Application
    Filed: January 2, 2019
    Publication date: May 23, 2019
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10199121
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: February 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Publication number: 20180306610
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Application
    Filed: June 25, 2018
    Publication date: October 25, 2018
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerard M. Salem, Tobias Webel
  • Publication number: 20180294042
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Application
    Filed: May 8, 2018
    Publication date: October 11, 2018
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Publication number: 20180294041
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Application
    Filed: December 27, 2017
    Publication date: October 11, 2018
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10096377
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Patent number: 10026498
    Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mitesh Agrawal, Benedikt Geukes, Krishnendu Mondal
  • Publication number: 20170261354
    Abstract: Embodiments include methods, and computer system, and computer program products for performing test and calibration of integrated sensors on a processor chip. Aspects include: initializing, by a tester program, an on-chip service engine of processor chip, performing and completing, by on-chip service engine, test and calibration of integrated sensors. The method may also include: loading and decoding tester program into an on-chip service engine memory, testing and calibrating each integrated sensor, which may include: selecting an integrated sensor for test and calibration, loading sensor test and calibration patterns and parameters, and sensor test code, and executing the sensor test code to test and calibrate integrated sensors, writing results of the test and calibration to a predetermined location of the on-chip service engine memory, and writing a return code of test and calibration to another predetermined location of on-chip service engine memory, when every integrated sensor is tested and calibrated.
    Type: Application
    Filed: March 8, 2016
    Publication date: September 14, 2017
    Inventors: Mitesh Agrawal, Preetham M. Lobo, Franco Motika, John D. Parker, Gerald M. Salem, Tobias Webel